isa/rv64sv/ma_vsd.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_vsd.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned vector sd trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64SV
  14 RVTEST_CODE_BEGIN
  15
  16   vsetcfg 32,0
  17   li a3,4
  18   vsetvl a3,a3
  19
  20   la a3, src1
  21   la a4, src2
  22   vld vx2,a3
  23   vld vx3,a4
  24   lui a0,%hi(vtcode1)
  25   vf %lo(vtcode1)(a0)
  26   la a3, dest+1
  27   vsd vx1, a3
  28   fence
  29
  30 vtcode1:
  31   add x2,x2,x3
  32   stop
  33
  34 vtcode2:
  35   add x2,x2,x3
  36   stop
  37
  38 stvec_handler:
  39   vxcptkill
  40
  41   li TESTNUM,2
  42
  43   # check cause
  44   csrr a3, scause
  45   li a4,HWACHA_CAUSE_MISALIGNED_STORE
  46   bne a3,a4,fail
  47
  48   # check vec irq aux
  49   csrr a3, sbadaddr
  50   la a4,dest+1
  51   bne a3,a4,fail
  52
  53   # make sure vector unit has cleared out
  54   vsetcfg 32,0
  55   li a3,4
  56   vsetvl a3,a3
  57
  58   la a3,src1
  59   la a4,src2
  60   vld vx2,a3
  61   vld vx3,a4
  62   lui a0,%hi(vtcode2)
  63   vf %lo(vtcode2)(a0)
  64   la a5,dest
  65   vsd vx2,a5
  66   fence
  67
  68   ld a1,0(a5)
  69   li a2,5
  70   li TESTNUM,2
  71   bne a1,a2,fail
  72   ld a1,8(a5)
  73   li TESTNUM,3
  74   bne a1,a2,fail
  75   ld a1,16(a5)
  76   li TESTNUM,4
  77   bne a1,a2,fail
  78   ld a1,24(a5)
  79   li TESTNUM,5
  80   bne a1,a2,fail
  81
  82   TEST_PASSFAIL
  83
  84 RVTEST_CODE_END
  85
  86   .data
  87 RVTEST_DATA_BEGIN
  88
  89   TEST_DATA
  90
  91 src1:
  92   .dword 1
  93   .dword 2
  94   .dword 3
  95   .dword 4
  96 src2:
  97   .dword 4
  98   .dword 3
  99   .dword 2
 100   .dword 1
 101 dest:
 102   .dword 0xdeadbeefcafebabe
 103   .dword 0xdeadbeefcafebabe
 104   .dword 0xdeadbeefcafebabe
 105   .dword 0xdeadbeefcafebabe
 106
 107 RVTEST_DATA_END