Add LICENSE
[riscv-tests.git] / isa / rv64sv / ma_vsd.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # ma_vsd.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test misaligned vector sd trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64S
14 RVTEST_CODE_BEGIN
15
16 li a0, SR_EA | SR_EI
17 csrs status, a0
18
19 la a3,handler
20 csrw evec,a3
21
22 csrr a3,status
23 li a4,(1 << IRQ_COP)
24 slli a4,a4,SR_IM_SHIFT
25 or a3,a3,a4 # enable IM[COP]
26 csrw status,a3
27
28 vsetcfg 32,0
29 li a3,4
30 vsetvl a3,a3
31
32 la a3, src1
33 la a4, src2
34 vld vx2,a3
35 vld vx3,a4
36 lui a0,%hi(vtcode1)
37 vf %lo(vtcode1)(a0)
38 la a3, dest+1
39 vsd vx1, a3
40 fence
41
42 vtcode1:
43 add x2,x2,x3
44 stop
45
46 vtcode2:
47 add x2,x2,x3
48 stop
49
50 handler:
51 vxcptkill
52
53 li TESTNUM,2
54
55 # check cause
56 vxcptcause a3
57 li a4,HWACHA_CAUSE_MISALIGNED_STORE
58 bne a3,a4,fail
59
60 # check vec irq aux
61 vxcptaux a3
62 la a4,dest+1
63 bne a3,a4,fail
64
65 # make sure vector unit has cleared out
66 vsetcfg 32,0
67 li a3,4
68 vsetvl a3,a3
69
70 la a3,src1
71 la a4,src2
72 vld vx2,a3
73 vld vx3,a4
74 lui a0,%hi(vtcode2)
75 vf %lo(vtcode2)(a0)
76 la a5,dest
77 vsd vx2,a5
78 fence
79
80 ld a1,0(a5)
81 li a2,5
82 li TESTNUM,2
83 bne a1,a2,fail
84 ld a1,8(a5)
85 li TESTNUM,3
86 bne a1,a2,fail
87 ld a1,16(a5)
88 li TESTNUM,4
89 bne a1,a2,fail
90 ld a1,24(a5)
91 li TESTNUM,5
92 bne a1,a2,fail
93
94 TEST_PASSFAIL
95
96 RVTEST_CODE_END
97
98 .data
99 RVTEST_DATA_BEGIN
100
101 TEST_DATA
102
103 src1:
104 .dword 1
105 .dword 2
106 .dword 3
107 .dword 4
108 src2:
109 .dword 4
110 .dword 3
111 .dword 2
112 .dword 1
113 dest:
114 .dword 0xdeadbeefcafebabe
115 .dword 0xdeadbeefcafebabe
116 .dword 0xdeadbeefcafebabe
117 .dword 0xdeadbeefcafebabe
118
119 RVTEST_DATA_END