isa/rv64sv/ma_vt_inst.S

   1 #*****************************************************************************
   2 # ma_vt_inst.S
   3 #-----------------------------------------------------------------------------
   4 #
   5 # Test misaligned vt instruction trap.
   6 #
   7
   8 #include "riscv_test.h"
   9 #include "test_macros.h"
  10
  11 RVTEST_RV64S
  12 RVTEST_CODE_BEGIN
  13
  14   mfpcr a3,cr0
  15   li a4,1
  16   slli a5,a4,8
  17   or a3,a3,a4 # enable traps
  18   mtpcr a3,cr0
  19
  20   la a3,handler
  21   mtpcr a3,cr3 # set exception handler
  22
  23   vsetcfg 32,0
  24   li a3,4
  25   vsetvl a3,a3
  26
  27   lui a0,%hi(vtcode1+2)
  28   vf %lo(vtcode1+2)(a0)
  29 1:      j 1b
  30
  31 vtcode1:
  32   add x2,x2,x3
  33   stop
  34
  35 handler:
  36   vxcptkill
  37
  38   li x28,2
  39
  40   # check cause
  41   mfpcr a3,cr6
  42   li a4,24
  43   bne a3,a4,fail
  44
  45   # check badvaddr
  46   mfpcr a3,cr2
  47   la a4,vtcode1+2
  48   bne a3,a4,fail
  49
  50   # make sure vector unit has cleared out
  51   vsetcfg 32,0
  52   li a3,4
  53   vsetvl a3,a3
  54
  55   la a3,src1
  56   la a4,src2
  57   vld vx2,a3
  58   vld vx3,a4
  59   lui a0,%hi(vtcode1)
  60   vf %lo(vtcode1)(a0)
  61   la a5,dest
  62   vsd vx2,a5
  63   fence
  64
  65   ld a1,0(a5)
  66   li a2,5
  67   li x28,2
  68   bne a1,a2,fail
  69   ld a1,8(a5)
  70   li x28,3
  71   bne a1,a2,fail
  72   ld a1,16(a5)
  73   li x28,4
  74   bne a1,a2,fail
  75   ld a1,24(a5)
  76   li x28,5
  77   bne a1,a2,fail
  78
  79   TEST_PASSFAIL
  80
  81 RVTEST_CODE_END
  82
  83   .data
  84 RVTEST_DATA_BEGIN
  85
  86   TEST_DATA
  87
  88 src1:
  89   .dword 1
  90   .dword 2
  91   .dword 3
  92   .dword 4
  93 src2:
  94   .dword 4
  95   .dword 3
  96   .dword 2
  97   .dword 1
  98 dest:
  99   .dword 0xdeadbeefcafebabe
 100   .dword 0xdeadbeefcafebabe
 101   .dword 0xdeadbeefcafebabe
 102   .dword 0xdeadbeefcafebabe
 103
 104 RVTEST_DATA_END