isa/rv64sv/ma_vt_inst.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_vt_inst.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned vt instruction trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64SV
  14 RVTEST_CODE_BEGIN
  15
  16   vsetcfg 32,0
  17   li a3,4
  18   vsetvl a3,a3
  19
  20   lui a0,%hi(vtcode1+2)
  21   vf %lo(vtcode1+2)(a0)
  22 1:      j 1b
  23
  24 vtcode1:
  25   add x2,x2,x3
  26   stop
  27
  28 stvec_handler:
  29   vxcptkill
  30
  31   li TESTNUM,2
  32
  33   # check cause
  34   csrr a3, scause
  35   li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH
  36   bne a3,a4,fail
  37
  38   # check badvaddr
  39   csrr a3, sbadaddr
  40   la a4,vtcode1+2
  41   andi a3, a3, -4 # mask off lower bits so that may
  42   andi a4, a4, -4 # ignore impl. specific behavior
  43   bne a3,a4,fail
  44
  45   # make sure vector unit has cleared out
  46   vsetcfg 32,0
  47   li a3,4
  48   vsetvl a3,a3
  49
  50   la a3,src1
  51   la a4,src2
  52   vld vx2,a3
  53   vld vx3,a4
  54   lui a0,%hi(vtcode1)
  55   vf %lo(vtcode1)(a0)
  56   la a5,dest
  57   vsd vx2,a5
  58   fence
  59
  60   ld a1,0(a5)
  61   li a2,5
  62   li TESTNUM,2
  63   bne a1,a2,fail
  64   ld a1,8(a5)
  65   li TESTNUM,3
  66   bne a1,a2,fail
  67   ld a1,16(a5)
  68   li TESTNUM,4
  69   bne a1,a2,fail
  70   ld a1,24(a5)
  71   li TESTNUM,5
  72   bne a1,a2,fail
  73
  74   TEST_PASSFAIL
  75
  76 RVTEST_CODE_END
  77
  78   .data
  79 RVTEST_DATA_BEGIN
  80
  81   TEST_DATA
  82
  83 src1:
  84   .dword 1
  85   .dword 2
  86   .dword 3
  87   .dword 4
  88 src2:
  89   .dword 4
  90   .dword 3
  91   .dword 2
  92   .dword 1
  93 dest:
  94   .dword 0xdeadbeefcafebabe
  95   .dword 0xdeadbeefcafebabe
  96   .dword 0xdeadbeefcafebabe
  97   .dword 0xdeadbeefcafebabe
  98
  99 RVTEST_DATA_END