Update to new privileged ISA
[riscv-tests.git] / isa / rv64sv / ma_vt_inst.S
1 #*****************************************************************************
2 # ma_vt_inst.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test misaligned vt instruction trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 li a0, SR_EA | SR_EI
15 csrs status, a0
16
17 la a3,handler
18 csrw evec,a3
19
20 csrr a3,status
21 li a4,(1 << IRQ_COP)
22 slli a4,a4,SR_IM_SHIFT
23 or a3,a3,a4 # enable IM[COP]
24 csrw status,a3
25
26 vsetcfg 32,0
27 li a3,4
28 vsetvl a3,a3
29
30 lui a0,%hi(vtcode1+2)
31 vf %lo(vtcode1+2)(a0)
32 1: j 1b
33
34 vtcode1:
35 add x2,x2,x3
36 stop
37
38 handler:
39 vxcptkill
40
41 li x28,2
42
43 # check cause
44 vxcptcause a3
45 li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH
46 bne a3,a4,fail
47
48 # check badvaddr
49 vxcptaux a3
50 la a4,vtcode1+2
51 bne a3,a4,fail
52
53 # make sure vector unit has cleared out
54 vsetcfg 32,0
55 li a3,4
56 vsetvl a3,a3
57
58 la a3,src1
59 la a4,src2
60 vld vx2,a3
61 vld vx3,a4
62 lui a0,%hi(vtcode1)
63 vf %lo(vtcode1)(a0)
64 la a5,dest
65 vsd vx2,a5
66 fence
67
68 ld a1,0(a5)
69 li a2,5
70 li x28,2
71 bne a1,a2,fail
72 ld a1,8(a5)
73 li x28,3
74 bne a1,a2,fail
75 ld a1,16(a5)
76 li x28,4
77 bne a1,a2,fail
78 ld a1,24(a5)
79 li x28,5
80 bne a1,a2,fail
81
82 TEST_PASSFAIL
83
84 RVTEST_CODE_END
85
86 .data
87 RVTEST_DATA_BEGIN
88
89 TEST_DATA
90
91 src1:
92 .dword 1
93 .dword 2
94 .dword 3
95 .dword 4
96 src2:
97 .dword 4
98 .dword 3
99 .dword 2
100 .dword 1
101 dest:
102 .dword 0xdeadbeefcafebabe
103 .dword 0xdeadbeefcafebabe
104 .dword 0xdeadbeefcafebabe
105 .dword 0xdeadbeefcafebabe
106
107 RVTEST_DATA_END