isa/rv64sv/privileged_inst.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # illegal_tvec_cmd.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test illegal tvec command trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64SV
  14 RVTEST_CODE_BEGIN
  15
  16   la a3,handler
  17   csrw stvec,a3 # set exception handler
  18
  19   li a3, SSTATUS_PS
  20   csrc sstatus, a3
  21   la t0, 1f
  22   csrw sepc, t0
  23   sret
  24 1:
  25
  26 privileged_inst:
  27   vxcptcause a3 # privileged inst
  28
  29 vtcode2:
  30   add x2,x2,x3
  31   stop
  32
  33 handler:
  34   vxcptkill
  35
  36   li TESTNUM,2
  37
  38   # check cause
  39   vxcptcause a3
  40   li a4,HWACHA_CAUSE_PRIVILEGED_INSTRUCTION
  41   bne a3,a4,fail
  42
  43   # check vec irq aux
  44   vxcptaux a3
  45   la a4, privileged_inst
  46   lw a5, 0(a4)
  47   bne a3,a5,fail
  48
  49   # make sure vector unit has cleared out
  50   vsetcfg 32,0
  51   li a3,4
  52   vsetvl a3,a3
  53
  54   la a3,src1
  55   la a4,src2
  56   vld vx2,a3
  57   vld vx3,a4
  58   lui a0,%hi(vtcode2)
  59   vf %lo(vtcode2)(a0)
  60   la a5,dest
  61   vsd vx2,a5
  62   fence
  63
  64   ld a1,0(a5)
  65   li a2,5
  66   li TESTNUM,2
  67   bne a1,a2,fail
  68   ld a1,8(a5)
  69   li TESTNUM,3
  70   bne a1,a2,fail
  71   ld a1,16(a5)
  72   li TESTNUM,4
  73   bne a1,a2,fail
  74   ld a1,24(a5)
  75   li TESTNUM,5
  76   bne a1,a2,fail
  77
  78   TEST_PASSFAIL
  79
  80 RVTEST_CODE_END
  81
  82   .data
  83 RVTEST_DATA_BEGIN
  84
  85   TEST_DATA
  86
  87 src1:
  88   .dword 1
  89   .dword 2
  90   .dword 3
  91   .dword 4
  92 src2:
  93   .dword 4
  94   .dword 3
  95   .dword 2
  96   .dword 1
  97 dest:
  98   .dword 0xdeadbeefcafebabe
  99   .dword 0xdeadbeefcafebabe
 100   .dword 0xdeadbeefcafebabe
 101   .dword 0xdeadbeefcafebabe
 102
 103 RVTEST_DATA_END