Check that SC yields the load reservation
[riscv-tests.git] / isa / rv64ua / lrsc.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # lrsr.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test LR/SC instructions.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64U
14 RVTEST_CODE_BEGIN
15
16 # get a unique core id
17 la a0, coreid
18 li a1, 1
19 amoadd.w a2, a1, (a0)
20
21 # for now, only run this on core 0
22 1:li a3, 1
23 bgeu a2, a3, 1b
24
25 1: lw a1, (a0)
26 bltu a1, a3, 1b
27
28 # make sure that sc without a reservation fails.
29 TEST_CASE( 2, a4, 1, \
30 la a0, foo; \
31 sc.w a4, x0, (a0); \
32 )
33
34 # make sure that sc with the wrong reservation fails.
35 # TODO is this actually mandatory behavior?
36 TEST_CASE( 3, a4, 1, \
37 la a0, foo; \
38 la a1, fooTest3; \
39 lr.w a1, (a1); \
40 sc.w a4, a1, (a0); \
41 )
42
43 #define LOG_ITERATIONS 10
44
45 # have each core add its coreid+1 to foo 1024 times
46 la a0, foo
47 li a1, 1<<LOG_ITERATIONS
48 addi a2, a2, 1
49 1: lr.w a4, (a0)
50 add a4, a4, a2
51 sc.w a4, a4, (a0)
52 bnez a4, 1b
53 add a1, a1, -1
54 bnez a1, 1b
55
56 # wait for all cores to finish
57 la a0, barrier
58 li a1, 1
59 amoadd.w x0, a1, (a0)
60 1: lw a1, (a0)
61 blt a1, a3, 1b
62 fence
63
64 # expected result is 512*ncores*(ncores+1)
65 TEST_CASE( 4, a0, 0, \
66 lw a0, foo; \
67 slli a1, a3, LOG_ITERATIONS-1; \
68 1:sub a0, a0, a1; \
69 addi a3, a3, -1; \
70 bgez a3, 1b
71 )
72
73 # make sure that sc-after-successful-sc fails.
74 TEST_CASE( 5, a1, 1, \
75 la a0, foo; \
76 1:lr.w a1, (a0); \
77 sc.w a1, x0, (a0); \
78 bnez a1, 1b; \
79 sc.w a1, x0, (a0)
80 )
81
82 TEST_PASSFAIL
83
84 RVTEST_CODE_END
85
86 .data
87 RVTEST_DATA_BEGIN
88
89 TEST_DATA
90
91 coreid: .word 0
92 barrier: .word 0
93 foo: .word 0
94 .skip 1024
95 fooTest3: .word 0
96 RVTEST_DATA_END