Merge pull request #21 from sifive/add_freedom_sim_targets
[riscv-tests.git] / isa / rv64ud / fclass.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # fclass.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test fclass.d instruction.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64UF
14 RVTEST_CODE_BEGIN
15
16 #-------------------------------------------------------------
17 # Arithmetic tests
18 #-------------------------------------------------------------
19
20 TEST_FCLASS_D( 2, 1 << 0, 0xfff0000000000000 )
21 TEST_FCLASS_D( 3, 1 << 1, 0xbff0000000000000 )
22 TEST_FCLASS_D( 4, 1 << 2, 0x800fffffffffffff )
23 TEST_FCLASS_D( 5, 1 << 3, 0x8000000000000000 )
24 TEST_FCLASS_D( 6, 1 << 4, 0x0000000000000000 )
25 TEST_FCLASS_D( 7, 1 << 5, 0x000fffffffffffff )
26 TEST_FCLASS_D( 8, 1 << 6, 0x3ff0000000000000 )
27 TEST_FCLASS_D( 9, 1 << 7, 0x7ff0000000000000 )
28 TEST_FCLASS_D(10, 1 << 8, 0x7ff0000000000001 )
29 TEST_FCLASS_D(11, 1 << 9, 0x7ff8000000000000 )
30
31 TEST_PASSFAIL
32
33 RVTEST_CODE_END
34
35 .data
36 RVTEST_DATA_BEGIN
37
38 TEST_DATA
39
40 RVTEST_DATA_END