isa/rv64ud/recoding.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # recoding.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test corner cases of John Hauser's microarchitectural recoding scheme.
   8 # There are twice as many recoded values as IEEE-754 values; some of these
   9 # extras are redundant (e.g. Inf) and others are illegal (subnormals with
  10 # too many bits set).
  11 #
  12
  13 #include "riscv_test.h"
  14 #include "test_macros.h"
  15
  16 RVTEST_RV64UF
  17 RVTEST_CODE_BEGIN
  18
  19   # Make sure infinities with different mantissas compare as equal.
  20   fld f0, minf, a0
  21   fld f1, three, a0
  22   fmul.d f1, f1, f0
  23   TEST_CASE( 2, a0, 1, feq.d a0, f0, f1)
  24   TEST_CASE( 3, a0, 1, fle.d a0, f0, f1)
  25   TEST_CASE( 4, a0, 0, flt.d a0, f0, f1)
  26
  27   # Likewise, but for zeroes.
  28   fcvt.d.w f0, x0
  29   li a0, 1
  30   fcvt.d.w f1, a0
  31   fmul.d f1, f1, f0
  32   TEST_CASE(5, a0, 1, feq.d a0, f0, f1)
  33   TEST_CASE(6, a0, 1, fle.d a0, f0, f1)
  34   TEST_CASE(7, a0, 0, flt.d a0, f0, f1)
  35
  36   # When converting small doubles to single-precision subnormals,
  37   # ensure that the extra precision is discarded.
  38   flw f0, big, a0
  39   fld f1, tiny, a0
  40   fcvt.s.d f1, f1
  41   fmul.s f0, f0, f1
  42   fmv.x.s a0, f0
  43   lw a1, small
  44   TEST_CASE(10, a0, 0, sub a0, a0, a1)
  45
  46   # Make sure FSD+FLD correctly saves and restores a single-precision value.
  47   flw f0, three, a0
  48   fadd.s f1, f0, f0
  49   fadd.s f0, f0, f0
  50   fsd f0, tiny, a0
  51   fld f0, tiny, a0
  52   TEST_CASE(20, a0, 1, feq.s a0, f0, f1)
  53
  54   TEST_PASSFAIL
  55
  56 RVTEST_CODE_END
  57
  58   .data
  59 RVTEST_DATA_BEGIN
  60
  61 minf: .double -Inf
  62 three: .double 3.0
  63 big: .float 1221
  64 small: .float 2.9133121e-37
  65 tiny: .double 2.3860049081905093e-40
  66
  67 RVTEST_DATA_END