Remove instruction width assumptions to support RVC
[riscv-tests.git] / isa / rv64uf / Makefrag
1 #=======================================================================
2 # Makefrag for rv64uf tests
3 #-----------------------------------------------------------------------
4
5 rv64uf_sc_tests = \
6 fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin fsgnj \
7 ldst move recoding \
8
9 rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests))
10 rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests))
11
12 spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests)