split up rv64uf and rv64ud isa tests
[riscv-tests.git] / isa / rv64uf / recoding.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # recoding.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test corner cases of John Hauser's microarchitectural recoding scheme.
8 # There are twice as many recoded values as IEEE-754 values; some of these
9 # extras are redundant (e.g. Inf) and others are illegal (subnormals with
10 # too many bits set).
11 #
12
13 #include "riscv_test.h"
14 #include "test_macros.h"
15
16 RVTEST_RV64UF
17 RVTEST_CODE_BEGIN
18
19 # Make sure infinities with different mantissas compare as equal.
20 flw f0, minf, a0
21 flw f1, three, a0
22 fmul.s f1, f1, f0
23 TEST_CASE( 2, a0, 1, feq.s a0, f0, f1)
24 TEST_CASE( 3, a0, 1, fle.s a0, f0, f1)
25 TEST_CASE( 4, a0, 0, flt.s a0, f0, f1)
26
27 # Likewise, but for zeroes.
28 fcvt.s.w f0, x0
29 li a0, 1
30 fcvt.s.w f1, a0
31 fmul.s f1, f1, f0
32 TEST_CASE(5, a0, 1, feq.s a0, f0, f1)
33 TEST_CASE(6, a0, 1, fle.s a0, f0, f1)
34 TEST_CASE(7, a0, 0, flt.s a0, f0, f1)
35
36 TEST_PASSFAIL
37
38 RVTEST_CODE_END
39
40 .data
41 RVTEST_DATA_BEGIN
42
43 minf: .float -Inf
44 three: .float 3.0
45
46 RVTEST_DATA_END