Enable LR/SC tests, even for uniprocessors
[riscv-tests.git] / isa / rv64ui / Makefrag
1 #=======================================================================
2 # Makefrag for rv64ui tests
3 #-----------------------------------------------------------------------
4
5 rv64ui_sc_tests = \
6 add addi addiw addw \
7 amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \
8 amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
9 lrsc \
10 and andi \
11 auipc \
12 beq bge bgeu blt bltu bne \
13 div divu divuw divw \
14 example simple \
15 fence_i \
16 j jal jalr \
17 lb lbu lh lhu lw lwu ld \
18 lui \
19 mul mulh mulhsu mulhu mulw \
20 or ori \
21 rem remu remuw remw \
22 sb sh sw sd \
23 sll slli slliw sllw \
24 slt slti sltiu sltu \
25 sra srai sraiw sraw \
26 srl srli srliw srlw \
27 sub subw \
28 xor xori \
29
30 rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests))
31 rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sc_tests))
32
33 spike_tests += $(rv64ui_p_tests) $(rv64ui_v_tests)