92b7bb65c1997d7ab6ce04ea0513dc3cb133a310
[riscv-tests.git] / isa / rv64ui / amoadd_d.S
1 #*****************************************************************************
2 # amoadd_d.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test amoadd.d instruction.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64U
12 RVTEST_CODE_BEGIN
13
14 TEST_CASE(2, a4, 0xffffffff80000000, \
15 li a0, 0xffffffff80000000; \
16 li a1, 0xfffffffffffff800; \
17 la a3, amo_operand; \
18 sd a0, 0(a3); \
19 nop; nop; nop; nop; \
20 nop; nop; nop; nop; \
21 nop; nop; nop; nop; \
22 nop; nop; nop; nop; \
23 nop; nop; nop; nop; \
24 nop; nop; nop; nop; \
25 nop; nop; nop; nop; \
26 amoadd.d a4, a1, 0(a3); \
27 )
28
29 TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3))
30
31 # try again after a cache miss
32 TEST_CASE(4, a4, 0xffffffff7ffff800, \
33 li a4, 16384; \
34 add a5, a3, a4; \
35 ld x0, 0(a5); \
36 add a5, a5, a4; \
37 ld x0, 0(a5); \
38 add a5, a5, a4; \
39 ld x0, 0(a5); \
40 add a5, a5, a4; \
41 ld x0, 0(a5); \
42 amoadd.d a4, a1, 0(a3); \
43 )
44
45 TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3))
46
47 TEST_PASSFAIL
48
49 RVTEST_CODE_END
50
51 .data
52 RVTEST_DATA_BEGIN
53
54 TEST_DATA
55
56 RVTEST_DATA_END
57
58 .bss
59 .align 3
60 amo_operand:
61 .dword 0