initial commit
[riscv-tests.git] / isa / rv64ui / amoor_w.S
1 #*****************************************************************************
2 # amoor.w.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test amoor.w instruction.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64U
12 RVTEST_CODE_BEGIN
13
14 TEST_CASE(2, a4, 0xffffffff80000000, \
15 li a0, 0xffffffff80000000; \
16 li a1, 0xfffffffffffff800; \
17 la a3, amo_operand; \
18 sd a0, 0(a3); \
19 nop; nop; nop; nop; \
20 nop; nop; nop; nop; \
21 nop; nop; nop; nop; \
22 nop; nop; nop; nop; \
23 nop; nop; nop; nop; \
24 nop; nop; nop; nop; \
25 nop; nop; nop; nop; \
26 amoor.w a4, a1, 0(a3); \
27 )
28
29 TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
30
31 # try again after a cache miss
32 TEST_CASE(4, a4, 0xfffffffffffff800, \
33 li a1, 1; \
34 li a4, 16384; \
35 add a5, a3, a4; \
36 lw x0, 0(a5); \
37 add a5, a5, a4; \
38 lw x0, 0(a5); \
39 add a5, a5, a4; \
40 lw x0, 0(a5); \
41 add a5, a5, a4; \
42 lw x0, 0(a5); \
43 amoor.w a4, a1, 0(a3); \
44 )
45
46 TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3))
47
48 TEST_PASSFAIL
49
50 RVTEST_CODE_END
51
52 .data
53 RVTEST_DATA_BEGIN
54
55 TEST_DATA
56
57 RVTEST_DATA_END
58
59 .bss
60 .align 3
61 amo_operand:
62 .dword 0
63 .skip 65536