Enable LR/SC tests, even for uniprocessors
[riscv-tests.git] / isa / rv64ui / bltu.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # bltu.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test bltu instruction.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64U
14 RVTEST_CODE_BEGIN
15
16 #-------------------------------------------------------------
17 # Branch tests
18 #-------------------------------------------------------------
19
20 # Each test checks both forward and backward branches
21
22 TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 );
23 TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff );
24 TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff );
25
26 TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 );
27 TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe );
28 TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 );
29 TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff );
30
31 #-------------------------------------------------------------
32 # Bypassing tests
33 #-------------------------------------------------------------
34
35 TEST_BR2_SRC12_BYPASS( 9, 0, 0, bltu, 0xf0000000, 0xefffffff );
36 TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff );
37 TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff );
38 TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff );
39 TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff );
40 TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff );
41
42 TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff );
43 TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff );
44 TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff );
45 TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff );
46 TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff );
47 TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff );
48
49 #-------------------------------------------------------------
50 # Test delay slot instructions not executed nor bypassed
51 #-------------------------------------------------------------
52
53 TEST_CASE( 21, x1, 3, \
54 li x1, 1; \
55 bltu x0, x1, 1f; \
56 addi x1, x1, 1; \
57 addi x1, x1, 1; \
58 addi x1, x1, 1; \
59 addi x1, x1, 1; \
60 1: addi x1, x1, 1; \
61 addi x1, x1, 1; \
62 )
63
64 TEST_PASSFAIL
65
66 RVTEST_CODE_END
67
68 .data
69 RVTEST_DATA_BEGIN
70
71 TEST_DATA
72
73 RVTEST_DATA_END