Merge branch 'master' of github.com:ucb-bar/riscv-tests
[riscv-tests.git] / isa / rv64ui / j.S
1 #*****************************************************************************
2 # j.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test j instruction.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64U
12 RVTEST_CODE_BEGIN
13
14 #-------------------------------------------------------------
15 # Test basic
16 #-------------------------------------------------------------
17
18 li TESTNUM, 2;
19 j test_2;
20 j fail;
21 test_2:
22
23 #-------------------------------------------------------------
24 # Test delay slot instructions not executed nor bypassed
25 #-------------------------------------------------------------
26
27 TEST_CASE( 3, x1, 3, \
28 li x1, 1; \
29 j 1f; \
30 addi x1, x1, 1; \
31 addi x1, x1, 1; \
32 addi x1, x1, 1; \
33 addi x1, x1, 1; \
34 1: addi x1, x1, 1; \
35 addi x1, x1, 1; \
36 )
37
38 TEST_PASSFAIL
39
40 RVTEST_CODE_END
41
42 .data
43 RVTEST_DATA_BEGIN
44
45 TEST_DATA
46
47 RVTEST_DATA_END