a7e3fe68a9e791f75f3adf6eb18f10c65288aba9
[riscv-tests.git] / isa / rv64ui / j.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # j.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test j instruction.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64U
14 RVTEST_CODE_BEGIN
15
16 #-------------------------------------------------------------
17 # Test basic
18 #-------------------------------------------------------------
19
20 li TESTNUM, 2;
21 j test_2;
22 j fail;
23 test_2:
24
25 #-------------------------------------------------------------
26 # Test delay slot instructions not executed nor bypassed
27 #-------------------------------------------------------------
28
29 TEST_CASE( 3, x1, 3, \
30 li x1, 1; \
31 j 1f; \
32 addi x1, x1, 1; \
33 addi x1, x1, 1; \
34 addi x1, x1, 1; \
35 addi x1, x1, 1; \
36 1: addi x1, x1, 1; \
37 addi x1, x1, 1; \
38 )
39
40 TEST_PASSFAIL
41
42 RVTEST_CODE_END
43
44 .data
45 RVTEST_DATA_BEGIN
46
47 TEST_DATA
48
49 RVTEST_DATA_END