Enable LR/SC tests, even for uniprocessors
[riscv-tests.git] / isa / rv64ui / jalr.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # jalr.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test jalr instruction.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64U
14 RVTEST_CODE_BEGIN
15
16 #-------------------------------------------------------------
17 # Test 2: Basic test
18 #-------------------------------------------------------------
19
20 test_2:
21 li TESTNUM, 2
22 li t0, 0
23 la t1, target_2
24
25 jalr t0, t1, 0
26 linkaddr_2:
27 j fail
28
29 target_2:
30 la t1, linkaddr_2
31 bne t0, t1, fail
32
33 #-------------------------------------------------------------
34 # Bypassing tests
35 #-------------------------------------------------------------
36
37 TEST_JALR_SRC1_BYPASS( 4, 0, jalr );
38 TEST_JALR_SRC1_BYPASS( 5, 1, jalr );
39 TEST_JALR_SRC1_BYPASS( 6, 2, jalr );
40
41 #-------------------------------------------------------------
42 # Test delay slot instructions not executed nor bypassed
43 #-------------------------------------------------------------
44
45 TEST_CASE( 7, t0, 4, \
46 li t0, 1; \
47 la t1, 1f; \
48 jr t1, -4; \
49 addi t0, t0, 1; \
50 addi t0, t0, 1; \
51 addi t0, t0, 1; \
52 addi t0, t0, 1; \
53 1: addi t0, t0, 1; \
54 addi t0, t0, 1; \
55 )
56
57 TEST_PASSFAIL
58
59 RVTEST_CODE_END
60
61 .data
62 RVTEST_DATA_BEGIN
63
64 TEST_DATA
65
66 RVTEST_DATA_END