c821165e05111f88430523e2a799862efe4eeaa1
[riscv-tests.git] / isa / rv64ui / jalr.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # jalr.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test jalr instruction.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64U
14 RVTEST_CODE_BEGIN
15
16 #-------------------------------------------------------------
17 # Test 2: Basic test
18 #-------------------------------------------------------------
19
20 test_2:
21 li TESTNUM, 2
22 li x31, 0
23 la x2, target_2
24
25 linkaddr_2:
26 jalr x19, x2, 0
27 nop
28 nop
29
30 j fail
31
32 target_2:
33 la x1, linkaddr_2
34 addi x1, x1, 4
35 bne x1, x19, fail
36
37 #-------------------------------------------------------------
38 # Test 3: Check r0 target and that r31 is not modified
39 #-------------------------------------------------------------
40
41 test_3:
42 li TESTNUM, 3
43 li x31, 0
44 la x3, target_3
45
46 linkaddr_3:
47 jalr x0, x3, 0
48 nop
49
50 j fail
51
52 target_3:
53 bne x31, x0, fail
54
55 #-------------------------------------------------------------
56 # Bypassing tests
57 #-------------------------------------------------------------
58
59 TEST_JALR_SRC1_BYPASS( 4, 0, jalr );
60 TEST_JALR_SRC1_BYPASS( 5, 1, jalr );
61 TEST_JALR_SRC1_BYPASS( 6, 2, jalr );
62
63 #-------------------------------------------------------------
64 # Test delay slot instructions not executed nor bypassed
65 #-------------------------------------------------------------
66
67 TEST_CASE( 7, x1, 4, \
68 li x1, 1; \
69 la x2, 1f;
70 jalr x19, x2, -4; \
71 addi x1, x1, 1; \
72 addi x1, x1, 1; \
73 addi x1, x1, 1; \
74 addi x1, x1, 1; \
75 1: addi x1, x1, 1; \
76 addi x1, x1, 1; \
77 )
78
79 TEST_PASSFAIL
80
81 RVTEST_CODE_END
82
83 .data
84 RVTEST_DATA_BEGIN
85
86 TEST_DATA
87
88 RVTEST_DATA_END