Enable LR/SC tests, even for uniprocessors
[riscv-tests.git] / isa / rv64ui / rdnpc.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # rdnpc_w.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test rdnpc instruction.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64U
14 RVTEST_CODE_BEGIN
15
16 TEST_CASE(2, a0, 4, \
17 rdnpc a0; \
18 jal 1f; \
19 1: sub a0, ra, a0; \
20 )
21
22 TEST_PASSFAIL
23
24 RVTEST_CODE_END
25
26 .data
27 RVTEST_DATA_BEGIN
28
29 TEST_DATA
30
31 RVTEST_DATA_END