Clear triggers during entry.
[riscv-tests.git] / isa / rv64ui / srliw.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # srliw.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test srliw instruction.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64U
14 RVTEST_CODE_BEGIN
15
16 #-------------------------------------------------------------
17 # Arithmetic tests
18 #-------------------------------------------------------------
19
20 TEST_IMM_OP( 2, srliw, 0xffffffff80000000, 0xffffffff80000000, 0 );
21 TEST_IMM_OP( 3, srliw, 0x0000000040000000, 0xffffffff80000000, 1 );
22 TEST_IMM_OP( 4, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
23 TEST_IMM_OP( 5, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
24 TEST_IMM_OP( 6, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
25
26 TEST_IMM_OP( 7, srliw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
27 TEST_IMM_OP( 8, srliw, 0x000000007fffffff, 0xffffffffffffffff, 1 );
28 TEST_IMM_OP( 9, srliw, 0x0000000001ffffff, 0xffffffffffffffff, 7 );
29 TEST_IMM_OP( 10, srliw, 0x000000000003ffff, 0xffffffffffffffff, 14 );
30 TEST_IMM_OP( 11, srliw, 0x0000000000000001, 0xffffffffffffffff, 31 );
31
32 TEST_IMM_OP( 12, srliw, 0x0000000021212121, 0x0000000021212121, 0 );
33 TEST_IMM_OP( 13, srliw, 0x0000000010909090, 0x0000000021212121, 1 );
34 TEST_IMM_OP( 14, srliw, 0x0000000000424242, 0x0000000021212121, 7 );
35 TEST_IMM_OP( 15, srliw, 0x0000000000008484, 0x0000000021212121, 14 );
36 TEST_IMM_OP( 16, srliw, 0x0000000000000000, 0x0000000021212121, 31 );
37
38 #-------------------------------------------------------------
39 # Source/Destination tests
40 #-------------------------------------------------------------
41
42 TEST_IMM_SRC1_EQ_DEST( 17, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
43
44 #-------------------------------------------------------------
45 # Bypassing tests
46 #-------------------------------------------------------------
47
48 TEST_IMM_DEST_BYPASS( 18, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
49 TEST_IMM_DEST_BYPASS( 19, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
50 TEST_IMM_DEST_BYPASS( 20, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
51
52 TEST_IMM_SRC1_BYPASS( 21, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
53 TEST_IMM_SRC1_BYPASS( 22, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
54 TEST_IMM_SRC1_BYPASS( 23, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
55
56 TEST_IMM_ZEROSRC1( 24, srliw, 0, 31 );
57 TEST_IMM_ZERODEST( 25, srliw, 31, 28 );
58
59 TEST_PASSFAIL
60
61 RVTEST_CODE_END
62
63 .data
64 RVTEST_DATA_BEGIN
65
66 TEST_DATA
67
68 RVTEST_DATA_END