isa/rv64ui/sv_addi_subvl.S

   1 #include "riscv_test.h"
   2 #include "sv_test_macros.h"
   3
   4 RVTEST_RV64U        # Define TVM used by program.
   5
   6
   7 # SV test: vector-vector add
   8 #
   9 # sets up x3 and x4 with data, sets VL to 2, and carries out
  10 # an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
  11
  12 # Test code region.
  13 RVTEST_CODE_BEGIN   # Start of test code.
  14
  15         SV_LD_DATA( x2, testdata   , 0)
  16         SV_LD_DATA( x3, testdata+8 , 0)
  17         SV_LD_DATA( x4, testdata+16, 0)
  18         SV_LD_DATA( x5, testdata+24, 0)
  19
  20         SET_SV_MVL(1)
  21         SET_SV_CSR(1, 3, 0, 3, 1)
  22         SET_SV_VL(1)
  23         SET_SV_SUBVL(2)
  24
  25         addi    x3, x3, 1
  26
  27         CLR_SV_CSRS()
  28         SET_SV_VL(1)
  29         SET_SV_MVL(1)
  30         SET_SV_SUBVL(1)
  31
  32         TEST_SV_IMM(x2, 1001) # should not be modified
  33         TEST_SV_IMM(x3, 42)
  34         TEST_SV_IMM(x4, 43)
  35         TEST_SV_IMM(x5, 1002) # should not be modified
  36
  37         RVTEST_PASS           # Signal success.
  38 fail:
  39         RVTEST_FAIL
  40 RVTEST_CODE_END     # End of test code.
  41
  42 # Input data section.
  43 # This section is optional, and this data is NOT saved in the output.
  44 .data
  45         .align 3
  46 testdata:
  47         .dword 1001
  48         .dword 41
  49         .dword 42
  50         .dword 1002
  51
  52 # Output data section.
  53 RVTEST_DATA_BEGIN   # Start of test output data region.
  54         .align 3
  55 result:
  56         .dword -1
  57         .dword -1
  58         .dword -1
  59 RVTEST_DATA_END     # End of test output data region.
  60