initial commit
[riscv-tests.git] / isa / rv64uv / amoand_w.S
1 #*****************************************************************************
2 # amoand_w.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test amoand.w instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64U
12 RVTEST_CODE_BEGIN
13
14 li a4,2048
15 vvcfgivl a4,a4,4,0
16
17 la a5,amodest
18 vmsv vx2,a5
19 lui a0,%hi(vtcode)
20 vf %lo(vtcode)(a0)
21 la a6,dest
22 vsw vx1,a6
23 fence.v.l
24
25 li a1,0
26 li a2,0
27 loop:
28 lw a0,0(a6)
29 addi x28,a1,2
30 bne a0,a2,fail
31 addi a6,a6,4
32 addi a1,a1,1
33 bne a1,a4,loop
34 j pass
35
36 vtcode:
37 li x3,-1
38 amoand.w x1,x3,0(x2)
39 stop
40
41 TEST_PASSFAIL
42
43 RVTEST_CODE_END
44
45 .data
46 RVTEST_DATA_BEGIN
47
48 TEST_DATA
49
50 amodest:
51 .word 0
52 dest:
53 .skip 16384
54
55 RVTEST_DATA_END