5215c3bcb085a6d0cea6a6dbb550fc60b558f031
[riscv-tests.git] / isa / rv64uv / amomin_d.S
1 #*****************************************************************************
2 # amomin_d.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test amomin.d instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64UV
12 RVTEST_CODE_BEGIN
13
14 vsetcfg 4,0
15 li a4,2048
16 vsetvl a4,a4
17
18 la a5,amodest
19 vmsv vx2,a5
20 lui a0,%hi(vtcode)
21 vf %lo(vtcode)(a0)
22 la a6,dest
23 vsd vx1,a6
24 fence
25
26 li a1,0
27 li a2,-1
28 loop:
29 ld a0,0(a5)
30 addi TESTNUM,a1,2
31 bne a0,a2,fail
32 addi a5,a5,8
33 addi a1,a1,1
34 addi a2,a2,-1
35 bne a1,a4,loop
36 j pass
37
38 vtcode:
39 utidx x3
40 slli x3, x3, 3
41 add x2, x2, x3
42 utidx x3
43 addi x3,x3,1
44 li x1,-1
45 mul x3,x3,x1
46 amomin.d x1,x3,0(x2)
47 stop
48
49 TEST_PASSFAIL
50
51 RVTEST_CODE_END
52
53 .data
54 RVTEST_DATA_BEGIN
55
56 TEST_DATA
57
58 amodest:
59 .skip 16384
60 dest:
61 .skip 16384
62
63 RVTEST_DATA_END