Add LICENSE
[riscv-tests.git] / isa / rv64uv / amomin_w.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # amomin_w.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test amomin.w instruction in a vf block.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64UV
14 RVTEST_CODE_BEGIN
15
16 vsetcfg 4,0
17 li a4,2048
18 vsetvl a4,a4
19
20 la a5,amodest
21 vmsv vx2,a5
22 lui a0,%hi(vtcode)
23 vf %lo(vtcode)(a0)
24 la a6,dest
25 vsw vx1,a6
26 fence
27
28 li a1,0
29 li a2,0
30 loop:
31 lw a0,0(a6)
32 addi TESTNUM,a1,2
33 bne a0,a2,fail
34 addi a6,a6,4
35 addi a1,a1,1
36 addi a2,a2,-1
37 bne a1,a4,loop
38 j pass
39
40 vtcode:
41 utidx x3
42 addi x3,x3,1
43 li x1,-1
44 mul x3,x3,x1
45 amomin.w x1,x3,0(x2)
46 stop
47
48 TEST_PASSFAIL
49
50 RVTEST_CODE_END
51
52 .data
53 RVTEST_DATA_BEGIN
54
55 TEST_DATA
56
57 amodest:
58 .word 0
59 dest:
60 .skip 16384
61
62 RVTEST_DATA_END