44260f2e1ffca1074c5e5a743a6cd033b431eeac
[riscv-tests.git] / isa / rv64uv / amomin_w.S
1 #*****************************************************************************
2 # amomin_w.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test amomin.w instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64UV
12 RVTEST_CODE_BEGIN
13
14 vsetcfg 4,0
15 li a4,2048
16 vsetvl a4,a4
17
18 la a5,amodest
19 vmsv vx2,a5
20 lui a0,%hi(vtcode)
21 vf %lo(vtcode)(a0)
22 la a6,dest
23 vsw vx1,a6
24 fence
25
26 li a1,0
27 li a2,0
28 loop:
29 lw a0,0(a6)
30 addi x28,a1,2
31 bne a0,a2,fail
32 addi a6,a6,4
33 addi a1,a1,1
34 addi a2,a2,-1
35 bne a1,a4,loop
36 j pass
37
38 vtcode:
39 utidx x3
40 addi x3,x3,1
41 li x1,-1
42 mul x3,x3,x1
43 amomin.w x1,x3,0(x2)
44 stop
45
46 TEST_PASSFAIL
47
48 RVTEST_CODE_END
49
50 .data
51 RVTEST_DATA_BEGIN
52
53 TEST_DATA
54
55 amodest:
56 .word 0
57 dest:
58 .skip 16384
59
60 RVTEST_DATA_END