Merge branch 'master' of github.com:ucb-bar/riscv-tests
[riscv-tests.git] / isa / rv64uv / amoswap_w.S
1 #*****************************************************************************
2 # amoswap_w.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test amoswap.w instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64UV
12 RVTEST_CODE_BEGIN
13
14 vsetcfg 4,0
15 li a4,2048
16 vsetvl a4,a4
17
18 la a5,amodest
19 vmsv vx2,a5
20 lui a0,%hi(vtcode)
21 vf %lo(vtcode)(a0)
22 la a6,dest
23 vsw vx1,a6
24 fence
25
26 li a1,0
27 loop:
28 lw a0,0(a6)
29 addi TESTNUM,a1,2
30 bne a0,a1,fail
31 addi a6,a6,4
32 addi a1,a1,1
33 bne a1,a4,loop
34 j pass
35
36 vtcode:
37 utidx x3
38 addi x3,x3,1
39 amoswap.w x1,x3,0(x2)
40 stop
41
42 TEST_PASSFAIL
43
44 RVTEST_CODE_END
45
46 .data
47 RVTEST_DATA_BEGIN
48
49 TEST_DATA
50
51 amodest:
52 .word 0
53 dest:
54 .skip 16384
55
56 RVTEST_DATA_END