correctly set SR_EA bit for all vector physical tests
[riscv-tests.git] / isa / rv64uv / fence.S
1 #*****************************************************************************
2 # fence.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test fence instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64UV
12 RVTEST_CODE_BEGIN
13
14 # make sure these don't choke at the beginning
15 fence
16 fence rw,io
17 fence io,rw
18 fence r,io
19 fence w,io
20 fence rw,i
21 fence rw,o
22
23 li a0,1
24 bne a0,x0,skip1
25 fence
26 skip1:
27
28 bne a0,x0,skip3
29 fence
30 skip3:
31
32 j pass
33
34 TEST_PASSFAIL
35
36 RVTEST_CODE_END
37
38 .data
39 RVTEST_DATA_BEGIN
40
41 TEST_DATA
42
43 src1:
44 .dword 1
45 .dword 2
46 .dword 3
47 .dword 4
48 src2:
49 .dword 4
50 .dword 3
51 .dword 2
52 .dword 1
53 dest:
54 .dword 0xdeadbeefcafebabe
55 .dword 0xdeadbeefcafebabe
56 .dword 0xdeadbeefcafebabe
57 .dword 0xdeadbeefcafebabe
58
59 RVTEST_DATA_END