correctly set SR_EA bit for all vector physical tests
[riscv-tests.git] / isa / rv64uv / fld.S
1 #*****************************************************************************
2 # fld.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test fld instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64UV
12 RVTEST_CODE_BEGIN
13
14 vsetcfg 4,1
15 li a4,512
16 vsetvl a4,a4
17
18 la a5,src
19 vmsv vx2,a5
20 lui a0,%hi(vtcode)
21 vf %lo(vtcode)(a0)
22 la a6,dest
23 vfsd vf0,a6
24 fence
25
26 li a2,0
27 loop:
28 ld a0,0(a6)
29 addi x28,a2,2
30 ld a1,0(a5)
31 bne a0,a1,fail
32 addi a6,a6,8
33 addi a5,a5,8
34 addi a2,a2,1
35 bne a2,a4,loop
36 j pass
37
38 vtcode:
39 utidx x3
40 slli x3,x3,3
41 add x2,x2,x3
42 fld f0,0(x2)
43 stop
44
45 TEST_PASSFAIL
46
47 RVTEST_CODE_END
48
49 .data
50 RVTEST_DATA_BEGIN
51
52 TEST_DATA
53
54 src:
55 #include "data_fd.h"
56
57 dest:
58 .skip 16384
59
60 RVTEST_DATA_END