Merge branch 'master' of github.com:ucb-bar/riscv-tests
[riscv-tests.git] / isa / rv64uv / fmovn.S
1 #*****************************************************************************
2 # fmovn.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test fmovn instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64UV
12 RVTEST_CODE_BEGIN
13
14 vsetcfg 4,2
15 li a6,2048
16 vsetvl a6,a6
17
18 lui a0,%hi(vtcode)
19 vf %lo(vtcode)(a0)
20 la a7,dest
21 vfsd vf0,a7
22 fence
23
24 li a1,0
25 li a2,-1
26 loop:
27 ld a0,0(a7)
28 slti a4,a1,10
29 slli a4,a4,63
30 srai a4,a4,63
31 and a5,a2,a4
32 addi TESTNUM,a1,2
33 bne a0,a5,fail
34 addi a7,a7,8
35 addi a1,a1,1
36 bne a1,a6,loop
37 j pass
38
39 vtcode:
40 utidx x1
41 slti x2,x1,10
42 li x1,-1
43 li x3,0
44 fmv.d.x f0,x3
45 fmv.d.x f1,x1
46 fmovn f0,x2,f1
47 stop
48
49 TEST_PASSFAIL
50
51 RVTEST_CODE_END
52
53 .data
54 RVTEST_DATA_BEGIN
55
56 TEST_DATA
57
58 dest:
59 .skip 16384
60
61 RVTEST_DATA_END