1b3a2dd71a70b1dda7e3dd1164ab586d93a38b2a
[riscv-tests.git] / isa / rv64uv / imul.S
1 #*****************************************************************************
2 # imul.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test imul instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64UV
12 RVTEST_CODE_BEGIN
13
14 vsetcfg 3,0
15 li a3,2048
16 vsetvl a3,a3
17
18 li a4,20
19 li s0,2
20 vmsv vx1,a4
21 lui a0,%hi(vtcode)
22 vf %lo(vtcode)(a0)
23
24 nop
25 nop
26 nop
27 nop
28 nop
29 nop
30 nop
31 nop
32 nop
33 nop
34 nop
35 nop
36 nop
37 nop
38 nop
39 nop
40 nop
41 nop
42 nop
43 nop
44 mul s1,a4,s0
45
46 la a5,dest
47 vsd vx1,a5
48 fence
49
50 li s2,40
51 li x28,2
52 bne s1,s2,fail
53
54 li a1,0
55 li a2,0
56 loop:
57 ld a0,0(a5)
58 addi x28,a2,3
59 bne a0,a1,fail
60 addi a5,a5,8
61 addi a1,a1,20
62 addi a2,a2,1
63 bne a2,a3,loop
64 j pass
65
66 vtcode:
67 utidx x2
68 mul x1,x2,x1
69 stop
70
71 TEST_PASSFAIL
72
73 RVTEST_CODE_END
74
75 .data
76 RVTEST_DATA_BEGIN
77
78 TEST_DATA
79
80 dest:
81 .skip 16384
82
83 RVTEST_DATA_END