Add a top-level make clean target.
[riscv-tests.git] / isa / rv64uv / imul.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # imul.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test imul instruction in a vf block.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64UV
14 RVTEST_CODE_BEGIN
15
16 vsetcfg 3,0
17 li a3,2048
18 vsetvl a3,a3
19
20 li a4,20
21 li s0,2
22 vmsv vx1,a4
23 lui a0,%hi(vtcode)
24 vf %lo(vtcode)(a0)
25
26 nop
27 nop
28 nop
29 nop
30 nop
31 nop
32 nop
33 nop
34 nop
35 nop
36 nop
37 nop
38 nop
39 nop
40 nop
41 nop
42 nop
43 nop
44 nop
45 nop
46 mul s1,a4,s0
47
48 la a5,dest
49 vsd vx1,a5
50 fence
51
52 li s2,40
53 li TESTNUM,2
54 bne s1,s2,fail
55
56 li a1,0
57 li a2,0
58 loop:
59 ld a0,0(a5)
60 addi TESTNUM,a2,3
61 bne a0,a1,fail
62 addi a5,a5,8
63 addi a1,a1,20
64 addi a2,a2,1
65 bne a2,a3,loop
66 j pass
67
68 vtcode:
69 utidx x2
70 mul x1,x2,x1
71 stop
72
73 TEST_PASSFAIL
74
75 RVTEST_CODE_END
76
77 .data
78 RVTEST_DATA_BEGIN
79
80 TEST_DATA
81
82 dest:
83 .skip 16384
84
85 RVTEST_DATA_END