initial commit
[riscv-tests.git] / isa / rv64uv / lh.S
1 #*****************************************************************************
2 # lh.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test lh instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64U
12 RVTEST_CODE_BEGIN
13
14 li a4,512
15 vvcfgivl a4,a4,16,0
16
17 la a5,src
18 vmsv vx2,a5
19 lui a0,%hi(vtcode)
20 vf %lo(vtcode)(a0)
21 la a6,dest
22 vsd vx1,a6
23 fence.v.l
24
25 li a2,0
26 loop:
27 ld a0,0(a6)
28 ld a1,0(a5)
29 sll a3,a1,48
30 sra a3,a3,48
31 addi x28,a2,2
32 bne a0,a3,fail
33 addi a6,a6,8
34 addi a5,a5,8
35 addi a2,a2,1
36 bne a2,a4,loop
37 j pass
38
39 vtcode:
40 utidx x3
41 slli x3,x3,3
42 add x2,x2,x3
43 lh x1,0(x2)
44 stop
45
46 TEST_PASSFAIL
47
48 RVTEST_CODE_END
49
50 .data
51 RVTEST_DATA_BEGIN
52
53 TEST_DATA
54
55 src:
56 #include "data_d.h"
57
58 dest:
59 .skip 16384
60
61 RVTEST_DATA_END