Add a top-level make clean target.
[riscv-tests.git] / isa / rv64uv / sb.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # sb.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test sb instruction in a vf block.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64UV
14 RVTEST_CODE_BEGIN
15
16 vsetcfg 16,0
17 li a4,512
18 vsetvl a4,a4
19
20 la a6,dest
21 li a2,0
22
23 initloop:
24 sd x0,0(a6)
25 addi a6,a6,8
26 addi a2,a2,1
27 bne a2,a4,initloop
28 fence
29
30 la a5,src
31 vld vx1,a5
32 la a6,dest
33 vmsv vx2,a6
34 lui a0,%hi(vtcode)
35 vf %lo(vtcode)(a0)
36 fence
37
38 li a2,0
39 loop:
40 ld a0,0(a6)
41 ld a1,0(a5)
42 sll a3,a1,56
43 srl a3,a3,56
44 addi TESTNUM,a2,2
45 bne a0,a3,fail
46 addi a6,a6,8
47 addi a5,a5,8
48 addi a2,a2,1
49 bne a2,a4,loop
50 j pass
51
52 vtcode:
53 utidx x3
54 slli x3,x3,3
55 add x2,x2,x3
56 sb x1,0(x2)
57 stop
58
59 TEST_PASSFAIL
60
61 RVTEST_CODE_END
62
63 .data
64 RVTEST_DATA_BEGIN
65
66 TEST_DATA
67
68 src:
69 #include "data_d.h"
70
71 dest:
72 .skip 16384
73
74 RVTEST_DATA_END