b9954edd76a66912da4cf5d465f2645601feb41d
[riscv-tests.git] / isa / rv64uv / sb.S
1 #*****************************************************************************
2 # sb.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test sb instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64UV
12 RVTEST_CODE_BEGIN
13
14 vsetcfg 16,0
15 li a4,512
16 vsetvl a4,a4
17
18 la a6,dest
19 li a2,0
20
21 initloop:
22 sd x0,0(a6)
23 addi a6,a6,8
24 addi a2,a2,1
25 bne a2,a4,initloop
26 fence
27
28 la a5,src
29 vld vx1,a5
30 la a6,dest
31 vmsv vx2,a6
32 lui a0,%hi(vtcode)
33 vf %lo(vtcode)(a0)
34 fence
35
36 li a2,0
37 loop:
38 ld a0,0(a6)
39 ld a1,0(a5)
40 sll a3,a1,56
41 srl a3,a3,56
42 addi TESTNUM,a2,2
43 bne a0,a3,fail
44 addi a6,a6,8
45 addi a5,a5,8
46 addi a2,a2,1
47 bne a2,a4,loop
48 j pass
49
50 vtcode:
51 utidx x3
52 slli x3,x3,3
53 add x2,x2,x3
54 sb x1,0(x2)
55 stop
56
57 TEST_PASSFAIL
58
59 RVTEST_CODE_END
60
61 .data
62 RVTEST_DATA_BEGIN
63
64 TEST_DATA
65
66 src:
67 #include "data_d.h"
68
69 dest:
70 .skip 16384
71
72 RVTEST_DATA_END