initial commit
[riscv-tests.git] / isa / rv64uv / sw.S
1 #*****************************************************************************
2 # sw.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test sw instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64U
12 RVTEST_CODE_BEGIN
13
14 li a4,512
15 vvcfgivl a4,a4,16,0
16
17 la a6,dest
18 li a2,0
19
20 initloop:
21 sd x0,0(a6)
22 addi a6,a6,8
23 addi a2,a2,1
24 bne a2,a4,initloop
25 fence
26
27 la a5,src
28 vld vx1,a5
29 la a6,dest
30 vmsv vx2,a6
31 lui a0,%hi(vtcode)
32 vf %lo(vtcode)(a0)
33 fence.v.l
34
35 li a2,0
36 loop:
37 ld a0,0(a6)
38 ld a1,0(a5)
39 sll a3,a1,32
40 srl a3,a3,32
41 addi x28,a2,2
42 bne a0,a3,fail
43 addi a6,a6,8
44 addi a5,a5,8
45 addi a2,a2,1
46 bne a2,a4,loop
47 j pass
48
49 vtcode:
50 utidx x3
51 slli x3,x3,3
52 add x2,x2,x3
53 sw x1,0(x2)
54 stop
55
56 TEST_PASSFAIL
57
58 RVTEST_CODE_END
59
60 .data
61 RVTEST_DATA_BEGIN
62
63 TEST_DATA
64
65 src:
66 #include "data_d.h"
67
68 dest:
69 .skip 16384
70
71 RVTEST_DATA_END