initial commit
[riscv-tests.git] / isa / rv64uv / vvadd_d.S
1 #*****************************************************************************
2 # vvadd_d.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test vvadd d.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64U
12 RVTEST_CODE_BEGIN
13
14 li a3,4
15 vvcfgivl a3,a3,32,0
16
17 la a3,src1
18 la a4,src2
19 vld vx2,a3
20 vld vx3,a4
21 lui a0,%hi(vtcode1)
22 vf %lo(vtcode1)(a0)
23 la a5,dest
24 vsd vx2,a5
25 fence.v.l
26
27 ld a1,0(a5)
28 li a2,5
29 li x28,2
30 bne a1,a2,fail
31 ld a1,8(a5)
32 li x28,3
33 bne a1,a2,fail
34 ld a1,16(a5)
35 li x28,4
36 bne a1,a2,fail
37 ld a1,24(a5)
38 li x28,5
39 bne a1,a2,fail
40
41 la a3,src1
42 vld vx4,a3
43 lui a0,%hi(vtcode2)
44 vf %lo(vtcode2)(a0)
45 la a5,dest
46 vsd vx4,a5
47 fence.v.l
48
49 ld a1,0(a5)
50 li a2,1
51 li x28,6
52 bne a1,a2,fail
53 ld a1,8(a5)
54 li a2,2
55 li x28,7
56 bne a1,a2,fail
57 ld a1,16(a5)
58 li a2,3
59 li x28,8
60 bne a1,a2,fail
61 ld a1,24(a5)
62 li a2,4
63 li x28,9
64 bne a1,a2,fail
65
66 la a3,src2
67 vld vx5,a3
68 lui a0,%hi(vtcode3)
69 vf %lo(vtcode3)(a0)
70 la a5,dest
71 vsd vx5,a5
72 fence.v.l
73
74 ld a1,0(a5)
75 li a2,4
76 li x28,6
77 bne a1,a2,fail
78 ld a1,8(a5)
79 li a2,3
80 li x28,7
81 bne a1,a2,fail
82 ld a1,16(a5)
83 li a2,2
84 li x28,8
85 bne a1,a2,fail
86 ld a1,24(a5)
87 li a2,1
88 li x28,9
89 bne a1,a2,fail
90
91 j pass
92
93 vtcode1:
94 add x2,x2,x3
95 stop
96
97 vtcode2:
98 add a0,a0,x0
99 stop
100
101 vtcode3:
102 add a1,a1,x0
103 stop
104
105 TEST_PASSFAIL
106
107 RVTEST_CODE_END
108
109 .data
110 RVTEST_DATA_BEGIN
111
112 TEST_DATA
113
114 src1:
115 .dword 1
116 .dword 2
117 .dword 3
118 .dword 4
119 src2:
120 .dword 4
121 .dword 3
122 .dword 2
123 .dword 1
124 dest:
125 .dword 0xdeadbeefcafebabe
126 .dword 0xdeadbeefcafebabe
127 .dword 0xdeadbeefcafebabe
128 .dword 0xdeadbeefcafebabe
129
130 RVTEST_DATA_END