Merge branch 'master' of github.com:ucb-bar/riscv-tests
[riscv-tests.git] / isa / rv64uv / vvadd_d.S
1 #*****************************************************************************
2 # vvadd_d.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test vvadd d.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64UV
12 RVTEST_CODE_BEGIN
13
14 vsetcfg 32,0
15 li a3,4
16 vsetvl a3,a3
17
18 la a3,src1
19 la a4,src2
20 vld vx2,a3
21 vld vx3,a4
22 lui a0,%hi(vtcode1)
23 vf %lo(vtcode1)(a0)
24 la a5,dest
25 vsd vx2,a5
26 fence
27
28 ld a1,0(a5)
29 li a2,5
30 li TESTNUM,2
31 bne a1,a2,fail
32 ld a1,8(a5)
33 li TESTNUM,3
34 bne a1,a2,fail
35 ld a1,16(a5)
36 li TESTNUM,4
37 bne a1,a2,fail
38 ld a1,24(a5)
39 li TESTNUM,5
40 bne a1,a2,fail
41
42 la a3,src1
43 vld vx4,a3
44 lui a0,%hi(vtcode2)
45 vf %lo(vtcode2)(a0)
46 la a5,dest
47 vsd vx4,a5
48 fence
49
50 ld a1,0(a5)
51 li a2,1
52 li TESTNUM,6
53 bne a1,a2,fail
54 ld a1,8(a5)
55 li a2,2
56 li TESTNUM,7
57 bne a1,a2,fail
58 ld a1,16(a5)
59 li a2,3
60 li TESTNUM,8
61 bne a1,a2,fail
62 ld a1,24(a5)
63 li a2,4
64 li TESTNUM,9
65 bne a1,a2,fail
66
67 la a3,src2
68 vld vx5,a3
69 lui a0,%hi(vtcode3)
70 vf %lo(vtcode3)(a0)
71 la a5,dest
72 vsd vx5,a5
73 fence
74
75 ld a1,0(a5)
76 li a2,4
77 li TESTNUM,6
78 bne a1,a2,fail
79 ld a1,8(a5)
80 li a2,3
81 li TESTNUM,7
82 bne a1,a2,fail
83 ld a1,16(a5)
84 li a2,2
85 li TESTNUM,8
86 bne a1,a2,fail
87 ld a1,24(a5)
88 li a2,1
89 li TESTNUM,9
90 bne a1,a2,fail
91
92 j pass
93
94 vtcode1:
95 add x2,x2,x3
96 stop
97
98 vtcode2:
99 add a0,a0,x0
100 stop
101
102 vtcode3:
103 add a1,a1,x0
104 stop
105
106 TEST_PASSFAIL
107
108 RVTEST_CODE_END
109
110 .data
111 RVTEST_DATA_BEGIN
112
113 TEST_DATA
114
115 src1:
116 .dword 1
117 .dword 2
118 .dword 3
119 .dword 4
120 src2:
121 .dword 4
122 .dword 3
123 .dword 2
124 .dword 1
125 dest:
126 .dword 0xdeadbeefcafebabe
127 .dword 0xdeadbeefcafebabe
128 .dword 0xdeadbeefcafebabe
129 .dword 0xdeadbeefcafebabe
130
131 RVTEST_DATA_END