correctly set SR_EA bit for all vector physical tests
[riscv-tests.git] / isa / rv64uv / vvadd_fw.S
1 #*****************************************************************************
2 # vvadd_fw.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test vvadd fw.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64UV
12 RVTEST_CODE_BEGIN
13
14 vsetcfg 32,32
15 li a3,4
16 vsetvl a3,a3
17
18 la a3,src1
19 la a4,src2
20 vflw vf2,a3
21 vflw vf3,a4
22 lui a0,%hi(vtcode)
23 vf %lo(vtcode)(a0)
24 la a5,dest
25 vfsw vf2,a5
26 fence
27 la a6,result
28 lw a1,0(a5)
29 lw a2,0(a6)
30 li x28,2
31 bne a1,a2,fail
32 lw a1,8(a5)
33 li x28,3
34 bne a1,a2,fail
35 lw a1,16(a5)
36 li x28,4
37 bne a1,a2,fail
38 lw a1,24(a5)
39 li x28,5
40 bne a1,a2,fail
41 j pass
42
43 vtcode:
44 fadd.s f2,f2,f3
45 stop
46
47 TEST_PASSFAIL
48
49 RVTEST_CODE_END
50
51 .data
52 RVTEST_DATA_BEGIN
53
54 TEST_DATA
55
56 src1:
57 .single 0.1
58 .single 0.2
59 .single 0.3
60 .single 0.4
61 src2:
62 .single 0.4
63 .single 0.3
64 .single 0.2
65 .single 0.1
66 dest:
67 .word 0xdeadbeef
68 .word 0xdeadbeef
69 .word 0xdeadbeef
70 .word 0xdeadbeef
71 result:
72 .single 0.5
73 .single 0.5
74 .single 0.5
75 .single 0.5
76
77 RVTEST_DATA_END