Add another FP recoding test case
[riscv-tests.git] / isa / rv64uv / vvadd_packed.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # vvadd_packed.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test packed half-precision vvadd
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64UV
14 RVTEST_CODE_BEGIN
15
16 li x1, 12 # number of test elements
17 move x10, x1
18 vsetucfg x2, 0x2
19 vsetcfg x2, 3, 1
20 loop:
21 vsetvl x4, x1
22 la x2, addr
23 vmsv vx1, x2
24 la x3, test
25 vf 0(x3)
26 sub x1, x1, x4
27 bnez x1, loop
28 fence
29 j check
30
31 enable_accel:
32 csrr x2, status
33 ori x2, x2, 0x100
34 csrw status, x2
35 # test if set
36 csrr x2, status
37 andi x2, x2, 0x100
38 beqz x2, fail
39 ret
40
41 enable_fp:
42 csrr x2, status
43 ori x2, x2, 0x10
44 csrw status, x2
45 # test if set
46 csrr x2, status
47 andi x2, x2, 0x10
48 beqz x2, fail
49 ret
50
51 test:
52 utidx x2
53 slli x2, x2, 2
54 add x1, x1, x2
55 flh f0, 0(x1)
56 fmul.h f0, f0, f0
57 fsh f0, 0(x1)
58 stop
59
60 check:
61 la x2, addr
62 la x4, expc
63
64 check_loop:
65 lw x3, 0(x4)
66 lw x1, 0(x2)
67 bne x1, x3, fail
68 addi x10, x10, -1
69 addi x4, x4, 0x4
70 addi x2, x2, 0x4
71 bnez x10, check_loop
72 j pass
73
74 TEST_PASSFAIL
75
76 .data
77 RVTEST_DATA_BEGIN
78
79 TEST_DATA
80
81 addr: .word 0x4000
82 .word 0x4400
83 .word 0x4800
84 .word 0x5000
85 .word 0x4001
86 .word 0x4401
87 .word 0x4801
88 .word 0x5001
89 .word 0x4002
90 .word 0x4402
91 .word 0x4802
92 .word 0x5002
93
94 expc: .word 0x4400
95 .word 0x4c00
96 .word 0x5400
97 .word 0x6400
98 .word 0x4402
99 .word 0x4c02
100 .word 0x5402
101 .word 0x6402
102 .word 0x4404
103 .word 0x4c04
104 .word 0x5404
105 .word 0x6404
106
107 RVTEST_DATA_END