correctly set SR_EA bit for all vector physical tests
[riscv-tests.git] / isa / rv64uv / vvadd_w.S
1 #*****************************************************************************
2 # vvadd_w.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test vvadd w.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64UV
12 RVTEST_CODE_BEGIN
13
14 vsetcfg 32,0
15 li a3,9
16 vsetvl a3,a3
17
18 la a3,src1
19 la a4,src2
20 vlw vx2,a3
21 vlw vx3,a4
22 lui a0,%hi(vtcode)
23 vf %lo(vtcode)(a0)
24 la a5,dest
25 vsw vx2,a5
26 fence
27 lw a1,0(a5)
28 li a2,10
29 li x28,2
30 bne a1,a2,fail
31 lw a1,4(a5)
32 li x28,3
33 bne a1,a2,fail
34 lw a1,8(a5)
35 li x28,4
36 bne a1,a2,fail
37 lw a1,12(a5)
38 li x28,5
39 bne a1,a2,fail
40 j pass
41
42 vtcode:
43 addw x2,x2,x3
44 stop
45
46 TEST_PASSFAIL
47
48 RVTEST_CODE_END
49
50 .data
51 RVTEST_DATA_BEGIN
52
53 TEST_DATA
54
55 src1:
56 .word 1
57 .word 2
58 .word 3
59 .word 4
60 .word 5
61 .word 6
62 .word 7
63 .word 8
64 .word 9
65 src2:
66 .word 9
67 .word 8
68 .word 7
69 .word 6
70 .word 5
71 .word 4
72 .word 3
73 .word 2
74 .word 1
75 dest:
76 .word 0xdeadbeef
77 .word 0xdeadbeef
78 .word 0xdeadbeef
79 .word 0xdeadbeef
80 .word 0xdeadbeef
81 .word 0xdeadbeef
82 .word 0xdeadbeef
83 .word 0xdeadbeef
84 .word 0xdeadbeef
85
86 RVTEST_DATA_END