isa/rv64uv/wakeup.S

   1 #*****************************************************************************
   2 # wakeup.S
   3 #-----------------------------------------------------------------------------
   4 #
   5 # Test wakeup.
   6 #
   7
   8 #include "riscv_test.h"
   9 #include "test_macros.h"
  10
  11 RVTEST_RV64UV
  12 RVTEST_CODE_BEGIN
  13
  14   # make sure these don't choke at the beginning
  15   fence
  16   fence rw,io
  17   fence io,rw
  18
  19   # this shouldn't go through since app vl is zero
  20   la a3,src1
  21   la a4,src2
  22   vld vx2,a3
  23   vld vx3,a4
  24   lui a0,%hi(vtcode1)
  25   vf %lo(vtcode1)(a0)
  26   la a5,dest
  27   vsd vx2,a5
  28   fence
  29
  30   ld a1,0(a5)
  31   li a2,0xdeadbeefcafebabe
  32   li x28,2
  33   bne a1,a2,fail
  34   ld a1,8(a5)
  35   li x28,3
  36   bne a1,a2,fail
  37   ld a1,16(a5)
  38   li x28,4
  39   bne a1,a2,fail
  40   ld a1,24(a5)
  41   li x28,5
  42   bne a1,a2,fail
  43
  44   # check default hw vector length, which is 32
  45   li a3, 32
  46   vsetvl a3, a3
  47   li a0, 32
  48   li x28, 6
  49   bne a3, a0, fail
  50
  51   li a3, 33
  52   vsetvl a3, a3
  53   li a0, 32
  54   li x28, 7
  55   bne a3, a0, fail
  56
  57   li a3, 31
  58   vsetvl a3, a3
  59   li a0, 31
  60   li x28, 8
  61   bne a3, a0, fail
  62
  63   # now do some vector stuff without vsetcfg
  64   vsetvl x0, x0
  65
  66   li a3, 4
  67   la a4,src1
  68   la a5,src2
  69   vsetvl a3, a3
  70   vld vx2,a4
  71   vld vx3,a5
  72   lui a0,%hi(vtcode1)
  73   vf %lo(vtcode1)(a0)
  74   la a5,dest
  75   vsd vx2,a5
  76   fence
  77
  78   ld a1,0(a5)
  79   li a2,5
  80   li x28,9
  81   bne a1,a2,fail
  82   ld a1,8(a5)
  83   li x28,10
  84   bne a1,a2,fail
  85   ld a1,16(a5)
  86   li x28,11
  87   bne a1,a2,fail
  88   ld a1,24(a5)
  89   li x28,12
  90   bne a1,a2,fail
  91
  92   # initialize dest memory
  93   li a3, 0xdeadbeefcafebabe
  94   sd a3, 0(a5)
  95   sd a3, 8(a5)
  96   sd a3, 16(a5)
  97   sd a3, 24(a5)
  98
  99   # test app vl zero again
 100   li a3, 0
 101   vsetvl a3, a3
 102
 103   la a3,src1
 104   la a4,src2
 105   vld vx2,a3
 106   vld vx3,a4
 107   lui a0,%hi(vtcode1)
 108   vf %lo(vtcode1)(a0)
 109   la a5,dest
 110   vsd vx2,a5
 111   fence
 112
 113   ld a1,0(a5)
 114   li a2,0xdeadbeefcafebabe
 115   li x28,13
 116   bne a1,a2,fail
 117   ld a1,8(a5)
 118   li x28,14
 119   bne a1,a2,fail
 120   ld a1,16(a5)
 121   li x28,15
 122   bne a1,a2,fail
 123   ld a1,24(a5)
 124   li x28,16
 125   bne a1,a2,fail
 126
 127   j pass
 128
 129 vtcode1:
 130   add x2,x2,x3
 131   stop
 132
 133   TEST_PASSFAIL
 134
 135 RVTEST_CODE_END
 136
 137   .data
 138 RVTEST_DATA_BEGIN
 139
 140   TEST_DATA
 141
 142 src1:
 143   .dword 1
 144   .dword 2
 145   .dword 3
 146   .dword 4
 147 src2:
 148   .dword 4
 149   .dword 3
 150   .dword 2
 151   .dword 1
 152 dest:
 153   .dword 0xdeadbeefcafebabe
 154   .dword 0xdeadbeefcafebabe
 155   .dword 0xdeadbeefcafebabe
 156   .dword 0xdeadbeefcafebabe
 157
 158 RVTEST_DATA_END