Merge pull request #1 from smirolo/configure
[riscv-tests.git] / mt / common / crt-mt.S
1 .data
2 .globl _heapend
3 .globl environ
4 _heapend:
5 .word 0
6 environ:
7 .word 0
8
9 .text
10 .globl _start
11
12 _start:
13 li x1, 0
14 li x2, 0
15 li x3, 0
16 li x4, 0
17 li x5, 0
18 li x6, 0
19 li x7, 0
20 li x8, 0
21 li x9, 0
22 li x10,0
23 li x11,0
24 li x12,0
25 li x13,0
26 li x14,0
27 li x15,0
28 li x16,0
29 li x17,0
30 li x18,0
31 li x19,0
32 li x20,0
33 li x21,0
34 li x22,0
35 li x23,0
36 li x24,0
37 li x25,0
38 li x26,0
39 li x27,0
40 li x28,0
41 li x29,0
42 li x30,0
43 li x31,0
44
45 # enable fp
46 mfpcr x1,cr0
47 ori x1,x1,0x2
48 mtpcr x1,cr0
49
50 # enable vec
51 mfpcr x1,cr0
52 ori x1,x1,0x4
53 mtpcr x1,cr0
54
55 ## if that didn't stick, we don't have an FPU, so don't initialize it
56 mfpcr x1,cr0
57 andi x1,x1,0x2
58 beqz x1,1f
59
60 mtfsr x0
61 mxtf.s f0, x0
62 mxtf.s f1, x0
63 mxtf.s f2, x0
64 mxtf.s f3, x0
65 mxtf.s f4, x0
66 mxtf.s f5, x0
67 mxtf.s f6, x0
68 mxtf.s f7, x0
69 mxtf.s f8, x0
70 mxtf.s f9, x0
71 mxtf.s f10,x0
72 mxtf.s f11,x0
73 mxtf.s f12,x0
74 mxtf.s f13,x0
75 mxtf.s f14,x0
76 mxtf.s f15,x0
77 mxtf.s f16,x0
78 mxtf.s f17,x0
79 mxtf.s f18,x0
80 mxtf.s f19,x0
81 mxtf.s f20,x0
82 mxtf.s f21,x0
83 mxtf.s f22,x0
84 mxtf.s f23,x0
85 mxtf.s f24,x0
86 mxtf.s f25,x0
87 mxtf.s f26,x0
88 mxtf.s f27,x0
89 mxtf.s f28,x0
90 mxtf.s f29,x0
91 mxtf.s f30,x0
92 mxtf.s f31,x0
93 1:
94
95 # get core id and number of cores
96 mfpcr a0,cr10
97 lw a1, 4(zero)
98
99 slli a2, a0, 13
100 la sp, stacktop
101 sub sp, sp, a2
102
103 la tp, tlstop
104 sub tp, tp, a2
105
106 jal thread_entry
107
108 .bss
109 .globl stacktop
110 .globl tlstop
111
112 .align 4
113 .skip 32768
114 stacktop:
115 .skip 65536
116 tlstop: