#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1)) #define SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \ (reg0 | (reg1<<8) | (reg2<<8) | \ (shape0<<24) | (shape0<<26) | (shape0<<28)) #define SV_SHAPE_PERM_XYZ 0 #define SV_SHAPE_PERM_XZY 1 #define SV_SHAPE_PERM_YXZ 2 #define SV_SHAPE_PERM_YZX 3 #define SV_SHAPE_PERM_ZXY 4 #define SV_SHAPE_PERM_ZYX 5 #define SV_SHAPE_CSR(xd, yd, zd, offs, perm) \ ((xd-1) | ((yd-1)<<8) | ((zd-1)<<16) | (perm<<24) | \ ((offs&0x1)<<7) | ((offs&0x2)<<14) | ((offs&0x4)<<21) ) #define SV_REG_CSR(type, regkey, elwidth, regidx, isvec) \ (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<15)) #define SV_PRED_CSR(type, regkey, zero, inv, regidx, packed) \ (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (packed<<15)) #define SET_SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \ li x1, SV_REMAP_CSR( reg0, shape0, reg1, shape1, reg2, shape2); \ csrrw x0, 0x4f7, x1 #define SET_SV_SHAPE0_CSR(xd, yd, zd, offs, permute) \ li x1, SV_SHAPE_CSR( xd, yd, zd, offs, permute); \ csrrw x0, 0x4f8, x1 // series of macros that set one, two or three register (or predicate) // key-value table entries that alter the behaviour of the registers #define SET_SV_CSR( type, regkey, elwidth, regidx, isvec) \ li x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \ csrrw x0, 0x4c0, x1 #define SET_SV_CSR2( type, regkey, elwidth, regidx, isvec) \ li x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \ csrrw x0, 0x4c1, x1 #define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ) \ li x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ); \ csrrw x0, 0x4c8, x1 #define SET_SV_2CSRS( c1, c2 ) \ li x1, c1 | ((c2)<<16U); \ csrrw x0, 0x4c0, x1 #define SET_SV_3CSRS( c1, c2 , c3 ) \ li x1, c1 | ((c2)<<16U) | ((c3)<<32U); \ csrrw x0, 0x4c0, x1 #define SET_SV_2PREDCSRS( c1, c2 ) \ li x1, c1 | ((c2)<<16U); \ csrrw x0, 0x4c8, x1 // clears the 2 CSRs set above #define CLR_SV_CSRS( ) csrrw x0, 0x4c0, 0; csrrw x0, 0x4c0, 0; csrrw x0, 0x4c0, 0; #define CLR_SV_PRED_CSRS( ) csrrw x0, 0x4c8, 0 // set maximum vector length. #define SET_SV_MVL( val ) csrrwi x0, 0x4f1, (val-1) // set actual vector length: normally that would // be vl = xN = min(mvl, min(vl, xN) however we // pass in x0 here. #define SET_SV_VL( val ) csrrwi x0, 0x4f0, (val-1) #define SV_LD_DATA( reg, from, offs ) \ la x1, from; \ lw reg, offs(x1) #define SV_LDD_DATA( reg, from, offs ) \ la x1, from; \ ld reg, offs(x1) #define SV_FLD_DATA( reg, from, offs ) \ la x1, from; \ fld reg, offs(x1) #define SV_FLW_DATA( reg, from, offs ) \ la x1, from; \ flw reg, offs(x1) #define TEST_SV_IMMW( reg, imm ) \ li t6, MASK_XLEN(imm) ; \ bne reg, t6, fail; #define TEST_SV_IMM( reg, imm ) \ li t6, ((imm) & 0xffffffffffffffff); \ bne reg, t6, fail; #define TEST_SV_FD( flags, freg, from, offs ) \ fsflags x2, x0; \ li x1, flags; \ bne x2, x1, fail; \ la x1, from; \ ld x1, offs(x1); \ fmv.x.d x2, freg; \ bne x2, x1, fail; #define TEST_SV_FW( flags, freg, from, offs ) \ fsflags x2, x0; \ li x1, flags; \ bne x2, x1, fail; \ la x1, from; \ lw x1, offs(x1); \ fmv.x.s x2, freg; \ bne x2, x1, fail; #define SV_W_DFLT 0 #define SV_W_8BIT 1 #define SV_W_16BIT 2 #define SV_W_32BIT 3