+# See LICENSE for license details.
+
#include "encoding.h"
#ifdef __riscv64
# define SREG sw
#endif
- .data
- .globl _heapend
- .globl environ
-_heapend:
- .word 0
-environ:
- .word 0
-
.text
- .globl _start
+ .align 6
+user_trap_entry:
+ j trap_entry
+
+ .align 6
+supervisor_trap_entry:
+ j supervisor_trap_entry
+ .align 6
+hypervisor_trap_entry:
+ j hypervisor_trap_entry
+
+ .align 6
+machine_trap_entry:
+ j trap_entry
+
+ .align 6
+ .globl _start
_start:
li x1, 0
li x2, 0
li x30,0
li x31,0
-#ifdef __riscv64
- li a0, SR_U64 | SR_S64
- csrs status, a0
+ li t0, MSTATUS_PRV1; csrc mstatus, t0 # run tests in user mode
+ li t0, MSTATUS_IE1; csrs mstatus, t0 # enable interrupts in user mode
+ li t0, MSTATUS_FS; csrs mstatus, t0 # enable FPU
+ li t0, MSTATUS_XS; csrs mstatus, t0 # enable accelerator
+
+#ifndef __riscv64
+ li t0, MSTATUS_UA; csrc mstatus, t0 # disable RV64 for user mode
#endif
- csrc status, SR_PS
- # enable fp and accelerator
- li a0, SR_EF | SR_EA
- csrs status, a0
+ csrr t0, mstatus
+ li t1, MSTATUS_XS
+ and t1, t0, t1
+ sw t1, have_vec, t2
- ## if that didn't stick, we don't have an FPU, so don't initialize it
- csrr t0, status
- and t0, t0, SR_EF
- beqz t0, 1f
+ ## if that didn't stick, we don't have a FPU, so don't initialize it
+ li t1, MSTATUS_FS
+ and t1, t0, t1
+ beqz t1, 1f
fssr x0
fmv.s.x f0, x0
fmv.s.x f31,x0
1:
- la t0, trap_entry
- csrw evec, t0
-
la tp, _end + 63
and tp, tp, -64
- # get core id and number of cores
+ # get core id
csrr a0, hartid
- lw a1, 4(zero)
+ # for now, assume only 1 core
+ li a1, 1
+1:bgeu a0, a1, 1b
# give each core 128KB of stack + TLS
#define STKSHIFT 17
sll sp, sp, STKSHIFT
add sp, sp, tp
- lui t0, %tprel_hi(tls_start)
- add t0, t0, %tprel_lo(tls_start)
- sub tp, tp, t0
-
la t0, _init
- csrw epc, t0
- sret
+ csrw mepc, t0
+ eret
trap_entry:
- csrw sup0, sp
- csrw sup1, t0
- csrr t0, status
- andi t0, t0, SR_PS
- bnez t0, 1f
- la sp, kstacktop
-1:
addi sp, sp, -272
- csrr t0, sup1
SREG x1, 8(sp)
SREG x2, 16(sp)
SREG x30, 240(sp)
SREG x31, 248(sp)
- csrr t0, sup0
- csrr t1, status
- SREG t0, 256(sp)
- SREG t1, 264(sp)
-
- csrr a0, cause
- csrr a1, epc
+ csrr a0, mcause
+ csrr a1, mepc
mv a2, sp
jal handle_trap
- csrw epc, v0
-
- LREG t0, 256(sp)
- LREG t1, 264(sp)
- csrw sup0, t0
- csrw status, t1
+ csrw mepc, a0
LREG x1, 8(sp)
LREG x2, 16(sp)
LREG x30, 240(sp)
LREG x31, 248(sp)
- csrr sp, sup0
- sret
+ addi sp, sp, 272
+ eret
+
+.section ".tdata.begin"
+.globl _tdata_begin
+_tdata_begin:
-.bss
-.align 4
-.skip 4096
-kstacktop:
+.section ".tdata.end"
+.globl _tdata_end
+_tdata_end:
-.section .tbss
-tls_start:
+.section ".tbss.end"
+.globl _tbss_end
+_tbss_end: