+# See LICENSE for license details.
+
#include "encoding.h"
- .data
- .globl _heapend
- .globl environ
-_heapend:
- .word 0
-environ:
- .word 0
+#ifdef __riscv64
+# define LREG ld
+# define SREG sd
+#else
+# define LREG lw
+# define SREG sw
+#endif
.text
- .globl _start
+ .align 6
+user_trap_entry:
+ j trap_entry
+
+ .align 6
+supervisor_trap_entry:
+ j supervisor_trap_entry
+
+ .align 6
+hypervisor_trap_entry:
+ j hypervisor_trap_entry
+ .align 6
+machine_trap_entry:
+ j trap_entry
+
+ .align 6
+ .globl _start
_start:
li x1, 0
li x2, 0
li x30,0
li x31,0
-#ifdef __riscv64
- li a0, SR_U64 | SR_S64
- csrs status, a0
+ li t0, MSTATUS_PRV1; csrc mstatus, t0 # run tests in user mode
+ li t0, MSTATUS_IE1; csrs mstatus, t0 # enable interrupts in user mode
+ li t0, MSTATUS_FS; csrs mstatus, t0 # enable FPU
+ li t0, MSTATUS_XS; csrs mstatus, t0 # enable accelerator
+
+#ifndef __riscv64
+ li t0, MSTATUS_UA; csrc mstatus, t0 # disable RV64 for user mode
#endif
- # enable fp and accelerator
- li a0, SR_EF | SR_EA
- csrs status, a0
+ csrr t0, mstatus
+ li t1, MSTATUS_XS
+ and t1, t0, t1
+ sw t1, have_vec, t2
- ## if that didn't stick, we don't have an FPU, so don't initialize it
- csrr t0, status
- and t0, t0, SR_EF
- beqz t0, 1f
+ ## if that didn't stick, we don't have a FPU, so don't initialize it
+ li t1, MSTATUS_FS
+ and t1, t0, t1
+ beqz t1, 1f
fssr x0
fmv.s.x f0, x0
fmv.s.x f31,x0
1:
- la t0, trap_entry
- csrw evec, t0
-
la tp, _end + 63
and tp, tp, -64
- # get core id and number of cores
+ # get core id
csrr a0, hartid
- lw a1, 4(zero)
+ # for now, assume only 1 core
+ li a1, 1
+1:bgeu a0, a1, 1b
- # give each core a 1KB TLS and a 127KB stack
+ # give each core 128KB of stack + TLS
#define STKSHIFT 17
sll a2, a0, STKSHIFT
add tp, tp, a2
add sp, a0, 1
sll sp, sp, STKSHIFT
add sp, sp, tp
- add tp, tp, 1024
- jal _init
- unimp
+ la t0, _init
+ csrw mepc, t0
+ eret
trap_entry:
- csrw sup0, t0
- csrw sup1, t1
- la t0, uarch_insn
- lw t0, (t0)
- csrr t1, epc
- and t1, t1, ~3
- lw t1, (t1)
- and t1, t1, t0
- beq t1, t0, handle_uarch_insn
-
- # a trap occurred that shouldn't have.
- li t0, 1337
- csrw tohost, t0
-1:j 1b
-
-handle_uarch_insn:
- # we trapped on an illegal uarch-specific CSR. just skip over it.
- csrr t1, epc
- add t1, t1, 4
- csrw epc, t1
- csrr t0, sup0
- csrr t1, sup1
- sret
-
-uarch_insn:
- csrr x0, uarch0
+ addi sp, sp, -272
+
+ SREG x1, 8(sp)
+ SREG x2, 16(sp)
+ SREG x3, 24(sp)
+ SREG x4, 32(sp)
+ SREG x5, 40(sp)
+ SREG x6, 48(sp)
+ SREG x7, 56(sp)
+ SREG x8, 64(sp)
+ SREG x9, 72(sp)
+ SREG x10, 80(sp)
+ SREG x11, 88(sp)
+ SREG x12, 96(sp)
+ SREG x13, 104(sp)
+ SREG x14, 112(sp)
+ SREG x15, 120(sp)
+ SREG x16, 128(sp)
+ SREG x17, 136(sp)
+ SREG x18, 144(sp)
+ SREG x19, 152(sp)
+ SREG x20, 160(sp)
+ SREG x21, 168(sp)
+ SREG x22, 176(sp)
+ SREG x23, 184(sp)
+ SREG x24, 192(sp)
+ SREG x25, 200(sp)
+ SREG x26, 208(sp)
+ SREG x27, 216(sp)
+ SREG x28, 224(sp)
+ SREG x29, 232(sp)
+ SREG x30, 240(sp)
+ SREG x31, 248(sp)
+
+ csrr a0, mcause
+ csrr a1, mepc
+ mv a2, sp
+ jal handle_trap
+ csrw mepc, a0
+
+ LREG x1, 8(sp)
+ LREG x2, 16(sp)
+ LREG x3, 24(sp)
+ LREG x4, 32(sp)
+ LREG x5, 40(sp)
+ LREG x6, 48(sp)
+ LREG x7, 56(sp)
+ LREG x8, 64(sp)
+ LREG x9, 72(sp)
+ LREG x10, 80(sp)
+ LREG x11, 88(sp)
+ LREG x12, 96(sp)
+ LREG x13, 104(sp)
+ LREG x14, 112(sp)
+ LREG x15, 120(sp)
+ LREG x16, 128(sp)
+ LREG x17, 136(sp)
+ LREG x18, 144(sp)
+ LREG x19, 152(sp)
+ LREG x20, 160(sp)
+ LREG x21, 168(sp)
+ LREG x22, 176(sp)
+ LREG x23, 184(sp)
+ LREG x24, 192(sp)
+ LREG x25, 200(sp)
+ LREG x26, 208(sp)
+ LREG x27, 216(sp)
+ LREG x28, 224(sp)
+ LREG x29, 232(sp)
+ LREG x30, 240(sp)
+ LREG x31, 248(sp)
+
+ addi sp, sp, 272
+ eret
+
+.section ".tdata.begin"
+.globl _tdata_begin
+_tdata_begin:
+
+.section ".tdata.end"
+.globl _tdata_end
+_tdata_end:
+
+.section ".tbss.end"
+.globl _tbss_end
+_tbss_end:
projects / riscv-tests.git / blobdiff