WIP on priv spec v1.9

[riscv-tests.git] / benchmarks / common / crt.S

diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S
index dc162287d127bc5748194881946e4fcbc64accdb..29c1d4dd1b08f90d617eee74e517daf993fc1a8c 100644 (file)
--- a/benchmarks/common/crt.S
+++ b/benchmarks/common/crt.S
@@ -5,9 +5,11 @@
 #ifdef __riscv64
 # define LREG ld
 # define SREG sd
+# define REGBYTES 8
 #else
 # define LREG lw
 # define SREG sw
+# define REGBYTES 4
 #endif
 
   .text
@@ -62,13 +64,13 @@ _start:
   li  x30,0
   li  x31,0
 
-  li t0, MSTATUS_PRV1; csrc mstatus, t0    # run tests in user mode
-  li t0, MSTATUS_IE1;  csrs mstatus, t0    # enable interrupts in user mode
+  li t0, MSTATUS_MPP;  csrc mstatus, t0    # run tests in user mode
+  li t0, MSTATUS_MPIE; csrs mstatus, t0    # enable interrupts in user mode
   li t0, MSTATUS_FS;   csrs mstatus, t0    # enable FPU
   li t0, MSTATUS_XS;   csrs mstatus, t0    # enable accelerator
 
 #ifdef __riscv64
-  csrr t0, mcpuid
+  csrr t0, misa
   # make sure processor supports RV64 if this was compiled for RV64
   bltz t0, 1f
   li a0, 1234
@@ -86,6 +88,7 @@ _start:
   and t1, t0, t1
   beqz t1, 1f
 
+#ifdef __riscv_hard_float
   fssr    x0
   fmv.s.x f0, x0
   fmv.s.x f1, x0
@@ -119,6 +122,8 @@ _start:
   fmv.s.x f29,x0
   fmv.s.x f30,x0
   fmv.s.x f31,x0
+#endif
+
 1:
 
   # initialize global pointer
@@ -148,37 +153,37 @@ _start:
 trap_entry:
   addi sp, sp, -272
 
-  SREG x1, 8(sp)
-  SREG x2, 16(sp)
-  SREG x3, 24(sp)
-  SREG x4, 32(sp)
-  SREG x5, 40(sp)
-  SREG x6, 48(sp)
-  SREG x7, 56(sp)
-  SREG x8, 64(sp)
-  SREG x9, 72(sp)
-  SREG x10, 80(sp)
-  SREG x11, 88(sp)
-  SREG x12, 96(sp)
-  SREG x13, 104(sp)
-  SREG x14, 112(sp)
-  SREG x15, 120(sp)
-  SREG x16, 128(sp)
-  SREG x17, 136(sp)
-  SREG x18, 144(sp)
-  SREG x19, 152(sp)
-  SREG x20, 160(sp)
-  SREG x21, 168(sp)
-  SREG x22, 176(sp)
-  SREG x23, 184(sp)
-  SREG x24, 192(sp)
-  SREG x25, 200(sp)
-  SREG x26, 208(sp)
-  SREG x27, 216(sp)
-  SREG x28, 224(sp)
-  SREG x29, 232(sp)
-  SREG x30, 240(sp)
-  SREG x31, 248(sp)
+  SREG x1, 1*REGBYTES(sp)
+  SREG x2, 2*REGBYTES(sp)
+  SREG x3, 3*REGBYTES(sp)
+  SREG x4, 4*REGBYTES(sp)
+  SREG x5, 5*REGBYTES(sp)
+  SREG x6, 6*REGBYTES(sp)
+  SREG x7, 7*REGBYTES(sp)
+  SREG x8, 8*REGBYTES(sp)
+  SREG x9, 9*REGBYTES(sp)
+  SREG x10, 10*REGBYTES(sp)
+  SREG x11, 11*REGBYTES(sp)
+  SREG x12, 12*REGBYTES(sp)
+  SREG x13, 13*REGBYTES(sp)
+  SREG x14, 14*REGBYTES(sp)
+  SREG x15, 15*REGBYTES(sp)
+  SREG x16, 16*REGBYTES(sp)
+  SREG x17, 17*REGBYTES(sp)
+  SREG x18, 18*REGBYTES(sp)
+  SREG x19, 19*REGBYTES(sp)
+  SREG x20, 20*REGBYTES(sp)
+  SREG x21, 21*REGBYTES(sp)
+  SREG x22, 22*REGBYTES(sp)
+  SREG x23, 23*REGBYTES(sp)
+  SREG x24, 24*REGBYTES(sp)
+  SREG x25, 25*REGBYTES(sp)
+  SREG x26, 26*REGBYTES(sp)
+  SREG x27, 27*REGBYTES(sp)
+  SREG x28, 28*REGBYTES(sp)
+  SREG x29, 29*REGBYTES(sp)
+  SREG x30, 30*REGBYTES(sp)
+  SREG x31, 31*REGBYTES(sp)
 
   csrr a0, mcause
   csrr a1, mepc
@@ -186,37 +191,37 @@ trap_entry:
   jal handle_trap
   csrw mepc, a0
 
-  LREG x1, 8(sp)
-  LREG x2, 16(sp)
-  LREG x3, 24(sp)
-  LREG x4, 32(sp)
-  LREG x5, 40(sp)
-  LREG x6, 48(sp)
-  LREG x7, 56(sp)
-  LREG x8, 64(sp)
-  LREG x9, 72(sp)
-  LREG x10, 80(sp)
-  LREG x11, 88(sp)
-  LREG x12, 96(sp)
-  LREG x13, 104(sp)
-  LREG x14, 112(sp)
-  LREG x15, 120(sp)
-  LREG x16, 128(sp)
-  LREG x17, 136(sp)
-  LREG x18, 144(sp)
-  LREG x19, 152(sp)
-  LREG x20, 160(sp)
-  LREG x21, 168(sp)
-  LREG x22, 176(sp)
-  LREG x23, 184(sp)
-  LREG x24, 192(sp)
-  LREG x25, 200(sp)
-  LREG x26, 208(sp)
-  LREG x27, 216(sp)
-  LREG x28, 224(sp)
-  LREG x29, 232(sp)
-  LREG x30, 240(sp)
-  LREG x31, 248(sp)
+  LREG x1, 1*REGBYTES(sp)
+  LREG x2, 2*REGBYTES(sp)
+  LREG x3, 3*REGBYTES(sp)
+  LREG x4, 4*REGBYTES(sp)
+  LREG x5, 5*REGBYTES(sp)
+  LREG x6, 6*REGBYTES(sp)
+  LREG x7, 7*REGBYTES(sp)
+  LREG x8, 8*REGBYTES(sp)
+  LREG x9, 9*REGBYTES(sp)
+  LREG x10, 10*REGBYTES(sp)
+  LREG x11, 11*REGBYTES(sp)
+  LREG x12, 12*REGBYTES(sp)
+  LREG x13, 13*REGBYTES(sp)
+  LREG x14, 14*REGBYTES(sp)
+  LREG x15, 15*REGBYTES(sp)
+  LREG x16, 16*REGBYTES(sp)
+  LREG x17, 17*REGBYTES(sp)
+  LREG x18, 18*REGBYTES(sp)
+  LREG x19, 19*REGBYTES(sp)
+  LREG x20, 20*REGBYTES(sp)
+  LREG x21, 21*REGBYTES(sp)
+  LREG x22, 22*REGBYTES(sp)
+  LREG x23, 23*REGBYTES(sp)
+  LREG x24, 24*REGBYTES(sp)
+  LREG x25, 25*REGBYTES(sp)
+  LREG x26, 26*REGBYTES(sp)
+  LREG x27, 27*REGBYTES(sp)
+  LREG x28, 28*REGBYTES(sp)
+  LREG x29, 29*REGBYTES(sp)
+  LREG x30, 30*REGBYTES(sp)
+  LREG x31, 31*REGBYTES(sp)
 
   addi sp, sp, 272
   eret