Fix FPU initialization code

[riscv-tests.git] / benchmarks / common / crt.S

diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S
index 7c8fc19c7df581c5e59f279437f30235653e6caf..3d4d6cff0bfdc97bb42a82d880859f71039f5665 100644 (file)
--- a/benchmarks/common/crt.S
+++ b/benchmarks/common/crt.S
@@ -2,7 +2,7 @@
 
 #include "encoding.h"
 
-#ifdef __riscv64
+#if __riscv_xlen == 64
 # define LREG ld
 # define SREG sd
 # define REGBYTES 8
@@ -12,12 +12,9 @@
 # define REGBYTES 4
 #endif
 
-  .text
+  .section ".text.init"
   .globl _start
 _start:
-  la t0, trap_entry
-  csrw mtvec, t0
-
   li  x1, 0
   li  x2, 0
   li  x3, 0
@@ -50,29 +47,29 @@ _start:
   li  x30,0
   li  x31,0
 
-  li t0, MSTATUS_FS;   csrs mstatus, t0    # enable FPU
-  li t0, MSTATUS_XS;   csrs mstatus, t0    # enable accelerator
+  # enable FPU and accelerator if present
+  li t0, MSTATUS_FS | MSTATUS_XS
+  csrs mstatus, t0
 
-#ifdef __riscv64
-  csrr t0, misa
-  # make sure processor supports RV64 if this was compiled for RV64
+  # make sure XLEN agrees with compilation choice
+  li t0, 1
+  slli t0, t0, 31
+#if __riscv_xlen == 64
+  bgez t0, 1f
+#else
   bltz t0, 1f
-  li a0, 1234
-  j tohost_exit
-1:
 #endif
+2:
+  li a0, 1
+  sw a0, tohost, t0
+  j 2b
+1:
 
-  csrr t0, mstatus
-  li t1, MSTATUS_XS
-  and t1, t0, t1
-  sw t1, have_vec, t2
-
-  ## if that didn't stick, we don't have a FPU, so don't initialize it
-  li t1, MSTATUS_FS
-  and t1, t0, t1
-  beqz t1, 1f
+#ifdef __riscv_flen
+  # initialize FPU if we have one
+  la t0, 1f
+  csrw mtvec, t0
 
-#ifdef __riscv_hard_float
   fssr    x0
   fmv.s.x f0, x0
   fmv.s.x f1, x0
@@ -106,9 +103,12 @@ _start:
   fmv.s.x f29,x0
   fmv.s.x f30,x0
   fmv.s.x f31,x0
+1:
 #endif
 
-1:
+  # initialize trap vector
+  la t0, trap_entry
+  csrw mtvec, t0
 
   # initialize global pointer
   la gp, _gp
@@ -132,6 +132,7 @@ _start:
 
   j _init
 
+  .align 2
 trap_entry:
   addi sp, sp, -272