Clean up benchmarks; support uarch-specific counters

[riscv-tests.git] / benchmarks / common / crt.S

diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S
index d1532104c5fed19369b6a4ff0fba1c359ab526b9..fb2cc25c692b4a8565d24dc12aa67e840dd0195e 100644 (file)
--- a/benchmarks/common/crt.S
+++ b/benchmarks/common/crt.S
@@ -1,3 +1,5 @@
+#include "encoding.h"
+
   .data
   .globl _heapend
   .globl environ
@@ -42,67 +44,101 @@ _start:
   li  x30,0
   li  x31,0
 
-  # enable fp
-  mfpcr  x1,cr0
-  ori  x1,x1,0x2
-  mtpcr  x1,cr0
+#ifdef __riscv64
+  li a0, SR_U64 | SR_S64
+  csrs status, a0
+#endif
 
-  # enable vec
-  mfpcr  x1,cr0
-  ori  x1,x1,0x4
-  mtpcr  x1,cr0
+  # enable fp and accelerator
+  li a0, SR_EF | SR_EA
+  csrs status, a0
 
   ## if that didn't stick, we don't have an FPU, so don't initialize it
-  mfpcr x1,cr0
-  andi x1,x1,0x2
-  beqz x1,1f
-
-  mtfsr   x0
-  mxtf.s  f0, x0
-  mxtf.s  f1, x0
-  mxtf.s  f2, x0
-  mxtf.s  f3, x0
-  mxtf.s  f4, x0
-  mxtf.s  f5, x0
-  mxtf.s  f6, x0
-  mxtf.s  f7, x0
-  mxtf.s  f8, x0
-  mxtf.s  f9, x0
-  mxtf.s  f10,x0
-  mxtf.s  f11,x0
-  mxtf.s  f12,x0
-  mxtf.s  f13,x0
-  mxtf.s  f14,x0
-  mxtf.s  f15,x0
-  mxtf.s  f16,x0
-  mxtf.s  f17,x0
-  mxtf.s  f18,x0
-  mxtf.s  f19,x0
-  mxtf.s  f20,x0
-  mxtf.s  f21,x0
-  mxtf.s  f22,x0
-  mxtf.s  f23,x0
-  mxtf.s  f24,x0
-  mxtf.s  f25,x0
-  mxtf.s  f26,x0
-  mxtf.s  f27,x0
-  mxtf.s  f28,x0
-  mxtf.s  f29,x0
-  mxtf.s  f30,x0
-  mxtf.s  f31,x0
+  csrr t0, status
+  and t0, t0, SR_EF
+  beqz t0, 1f
+
+  fssr    x0
+  fmv.s.x f0, x0
+  fmv.s.x f1, x0
+  fmv.s.x f2, x0
+  fmv.s.x f3, x0
+  fmv.s.x f4, x0
+  fmv.s.x f5, x0
+  fmv.s.x f6, x0
+  fmv.s.x f7, x0
+  fmv.s.x f8, x0
+  fmv.s.x f9, x0
+  fmv.s.x f10,x0
+  fmv.s.x f11,x0
+  fmv.s.x f12,x0
+  fmv.s.x f13,x0
+  fmv.s.x f14,x0
+  fmv.s.x f15,x0
+  fmv.s.x f16,x0
+  fmv.s.x f17,x0
+  fmv.s.x f18,x0
+  fmv.s.x f19,x0
+  fmv.s.x f20,x0
+  fmv.s.x f21,x0
+  fmv.s.x f22,x0
+  fmv.s.x f23,x0
+  fmv.s.x f24,x0
+  fmv.s.x f25,x0
+  fmv.s.x f26,x0
+  fmv.s.x f27,x0
+  fmv.s.x f28,x0
+  fmv.s.x f29,x0
+  fmv.s.x f30,x0
+  fmv.s.x f31,x0
 1:
 
-  # only allow core 0 to proceed
-1:mfpcr a0, cr10
-  bnez a0, 1b
+  la t0, trap_entry
+  csrw evec, t0
+
+  la  tp, _end + 63
+  and tp, tp, -64
+
+  # get core id and number of cores
+  csrr a0, hartid
+  lw a1, 4(zero)
+
+  # give each core a 1KB TLS and a 127KB stack
+#define STKSHIFT 17
+  sll a2, a0, STKSHIFT
+  add tp, tp, a2
+  add sp, a0, 1
+  sll sp, sp, STKSHIFT
+  add sp, sp, tp
+  add tp, tp, 1024
+
+  jal _init
+  unimp
+
+trap_entry:
+  csrw sup0, t0
+  csrw sup1, t1
+  la t0, uarch_insn
+  lw t0, (t0)
+  csrr t1, epc
+  and t1, t1, ~3
+  lw t1, (t1)
+  and t1, t1, t0
+  beq t1, t0, handle_uarch_insn
 
-  la  sp,stacktop
-  jal main
-1:b 1b
+  # a trap occurred that shouldn't have.
+  li t0, 1337
+  csrw tohost, t0
+1:j 1b
 
-  .bss
-  .globl stacktop
+handle_uarch_insn:
+  # we trapped on an illegal uarch-specific CSR.  just skip over it.
+  csrr t1, epc
+  add t1, t1, 4
+  csrw epc, t1
+  csrr t0, sup0
+  csrr t1, sup1
+  sret
 
-  .align 4
-  .skip 131072
-stacktop:
+uarch_insn:
+  csrr x0, uarch0