+// See LICENSE for license details.
+
#include <stdint.h>
#include <string.h>
#include <stdarg.h>
#include <stdio.h>
#include <limits.h>
-#include <machine/syscall.h>
-#include "encoding.h"
+#include "util.h"
+#define SYS_write 64
+#define SYS_exit 93
#define SYS_stats 1234
-#define static_assert(cond) switch(0) { case 0: case !!(long)(cond): ; }
+
+// initialized in crt.S
+int have_vec;
+
+extern volatile uint64_t tohost;
+extern volatile uint64_t fromhost;
static long handle_frontend_syscall(long which, long arg0, long arg1, long arg2)
{
magic_mem[2] = arg1;
magic_mem[3] = arg2;
__sync_synchronize();
- write_csr(tohost, (long)magic_mem);
- while (swap_csr(fromhost, 0) == 0);
+
+ tohost = (uintptr_t)magic_mem;
+ while (fromhost == 0)
+ ;
+ fromhost = 0;
+
+ __sync_synchronize();
return magic_mem[0];
}
// In setStats, we might trap reading uarch-specific counters.
// The trap handler will skip over the instruction and write 0,
-// but only if v0 is the destination register.
-#define read_csr_safe(reg) ({ register long __tmp asm("v0"); \
+// but only if a0 is the destination register.
+#define read_csr_safe(reg) ({ register long __tmp asm("a0"); \
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
__tmp; })
if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \
counters[i++] = csr; \
} while (0)
- READ_CTR(cycle); READ_CTR(instret);
- READ_CTR(uarch0); READ_CTR(uarch1); READ_CTR(uarch2); READ_CTR(uarch3);
- READ_CTR(uarch4); READ_CTR(uarch5); READ_CTR(uarch6); READ_CTR(uarch7);
- READ_CTR(uarch8); READ_CTR(uarch9); READ_CTR(uarch10); READ_CTR(uarch11);
- READ_CTR(uarch12); READ_CTR(uarch13); READ_CTR(uarch14); READ_CTR(uarch15);
+ READ_CTR(mcycle); READ_CTR(minstret);
+ READ_CTR(0xcc0); READ_CTR(0xcc1); READ_CTR(0xcc2); READ_CTR(0xcc3);
+ READ_CTR(0xcc4); READ_CTR(0xcc5); READ_CTR(0xcc6); READ_CTR(0xcc7);
+ READ_CTR(0xcc8); READ_CTR(0xcc9); READ_CTR(0xcca); READ_CTR(0xccb);
+ READ_CTR(0xccc); READ_CTR(0xccd); READ_CTR(0xcce); READ_CTR(0xccf);
#undef READ_CTR
return 0;
}
-static void tohost_exit(int code)
+void tohost_exit(long code)
{
- write_csr(tohost, (code << 1) | 1);
+ tohost = (code << 1) | 1;
while (1);
}
long handle_trap(long cause, long epc, long regs[32])
{
- int csr_insn;
- asm volatile ("lw %0, 1f; j 2f; 1: csrr v0, uarch0; 2:" : "=r"(csr_insn));
+ int* csr_insn;
+ asm ("jal %0, 1f; csrr a0, 0xcc0; 1:" : "=r"(csr_insn));
long sys_ret = 0;
if (cause == CAUSE_ILLEGAL_INSTRUCTION &&
- (*(int*)epc & csr_insn) == csr_insn)
+ (*(int*)epc & *csr_insn) == *csr_insn)
;
- else if (cause != CAUSE_SYSCALL)
+ else if (cause != CAUSE_MACHINE_ECALL)
tohost_exit(1337);
- else if (regs[16] == SYS_exit)
- tohost_exit(regs[18]);
- else if (regs[16] == SYS_stats)
- sys_ret = handle_stats(regs[18]);
+ else if (regs[17] == SYS_exit)
+ tohost_exit(regs[10]);
+ else if (regs[17] == SYS_stats)
+ sys_ret = handle_stats(regs[10]);
else
- sys_ret = handle_frontend_syscall(regs[16], regs[18], regs[19], regs[20]);
+ sys_ret = handle_frontend_syscall(regs[17], regs[10], regs[11], regs[12]);
- regs[16] = sys_ret;
+ regs[10] = sys_ret;
return epc+4;
}
static long syscall(long num, long arg0, long arg1, long arg2)
{
- register long v0 asm("v0") = num;
+ register long a7 asm("a7") = num;
register long a0 asm("a0") = arg0;
register long a1 asm("a1") = arg1;
register long a2 asm("a2") = arg2;
- asm volatile ("scall" : "+r"(v0) : "r"(a0), "r"(a1), "r"(a2) : "s0");
- return v0;
+ asm volatile ("scall" : "+r"(a0) : "r"(a1), "r"(a2), "r"(a7));
+ return a0;
}
void exit(int code)
{
syscall(SYS_exit, code, 0, 0);
+ while (1);
}
void setStats(int enable)
return -1;
}
+static void init_tls()
+{
+ register void* thread_pointer asm("tp");
+ extern char _tls_data;
+ extern __thread char _tdata_begin, _tdata_end, _tbss_end;
+ size_t tdata_size = &_tdata_end - &_tdata_begin;
+ memcpy(thread_pointer, &_tls_data, tdata_size);
+ size_t tbss_size = &_tbss_end - &_tdata_end;
+ memset(thread_pointer + tdata_size, 0, tbss_size);
+}
+
void _init(int cid, int nc)
{
+ init_tls();
thread_entry(cid, nc);
// only single-threaded programs should ever get here.
#undef putchar
int putchar(int ch)
{
- static char buf[64] __attribute__((aligned(64)));
- static int buflen = 0;
+ static __thread char buf[64] __attribute__((aligned(64)));
+ static __thread int buflen = 0;
buf[buflen++] = ch;
va_end(ap);
return str - str0;
}
+
+void* memcpy(void* dest, const void* src, size_t len)
+{
+ if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) {
+ const uintptr_t* s = src;
+ uintptr_t *d = dest;
+ while (d < (uintptr_t*)(dest + len))
+ *d++ = *s++;
+ } else {
+ const char* s = src;
+ char *d = dest;
+ while (d < (char*)(dest + len))
+ *d++ = *s++;
+ }
+ return dest;
+}
+
+void* memset(void* dest, int byte, size_t len)
+{
+ if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) {
+ uintptr_t word = byte & 0xFF;
+ word |= word << 8;
+ word |= word << 16;
+ word |= word << 16 << 16;
+
+ uintptr_t *d = dest;
+ while (d < (uintptr_t*)(dest + len))
+ *d++ = word;
+ } else {
+ char *d = dest;
+ while (d < (char*)(dest + len))
+ *d++ = byte;
+ }
+ return dest;
+}
+
+size_t strlen(const char *s)
+{
+ const char *p = s;
+ while (*p)
+ p++;
+ return p - s;
+}
+
+size_t strnlen(const char *s, size_t n)
+{
+ const char *p = s;
+ while (n-- && *p)
+ p++;
+ return p - s;
+}
+
+int strcmp(const char* s1, const char* s2)
+{
+ unsigned char c1, c2;
+
+ do {
+ c1 = *s1++;
+ c2 = *s2++;
+ } while (c1 != 0 && c1 == c2);
+
+ return c1 - c2;
+}
+
+char* strcpy(char* dest, const char* src)
+{
+ char* d = dest;
+ while ((*d++ = *src++))
+ ;
+ return dest;
+}
+
+long atol(const char* str)
+{
+ long res = 0;
+ int sign = 0;
+
+ while (*str == ' ')
+ str++;
+
+ if (*str == '-' || *str == '+') {
+ sign = *str == '-';
+ str++;
+ }
+
+ while (*str) {
+ res *= 10;
+ res += *str++ - '0';
+ }
+
+ return sign ? -res : res;
+}
projects / riscv-tests.git / blobdiff